CC2564C Datasheet, PDF (27/52 Pages) Texas Instruments – CC2564C Dual-Mode Bluetooth Controller

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CC2564C
SWRS199A – APRIL 2016 – REVISED NOVEMBER 2016
6.4 Functional Blocks
6.4.1 RF
The CC2564C device is the third generation of Bluetooth single-chip devices using DRP architecture from
TI. Modifications and new features added to the DRP further improve radio performance.
Figure 6-9 shows the DRP block diagram.
Transmitter path
Amplitude
TX digital data
Digital
ADPLL
DPA
Phase
Receiver path
RX digital data
Demodulation
ADC
IFA
Filter
LNA
SWRS092-005
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Figure 6-9. DRP Block Diagram
6.4.1.1 Receiver
The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal
received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a
mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by
a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.
The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an
adaptive-decision mechanism. The demodulator includes EDR processing with:
• State-of-the-art performance
• A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK
sensitivity
• Adaptive equalization to enhance EDR modulation
New features include:
• LNA input range narrowed to increase blocking performance
• Active spur cancellation to increase robustness to spurs
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