TLC59711 Datasheet, PDF (29/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
www.ti.com
SBVS181 – OCTOBER 2011
There is another control procedure that is recommended for a long chain of cascaded devices. The data and
clock timings are shown in Figure 9 and Figure 35. When 256 TLC59711 units are cascaded, use the following
procedure:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet MSB-first for the 256th TLC59711 using the SDTI and SCKI signals. The
EXTCLK bit must be set to '1' for the external oscillator mode. Also, the DSPRPT bit should be set to '0' so
that the PWM control does not repeat, the TMGRST bit should be set to '1' to reset the PWM control timing
with the internal latch pulse, and BLANK must be set to '0' to start the PWM control.
3. Repeat the data write sequence for all TLC59711s. The total shift clock count (SCKI) is 57344 (224 × 256).
After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between
the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift
resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34µs or more from step 3 (or step
7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC59711s for the next display with 256 × 224 SCKI
clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and
one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for
PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and
the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the
218-bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.
VLED Power
Shift Data From
Controller (SDTI)
Shift Clock From
Controller (SCKI)
Latch Pulse
(Internal)
MSB
LSB
224-Bit Packet for for
256th TLC59711 255th
MSB
The next shift clock should start after 1.34 ms or more from the internal latch pulse generation timing.
MSB
LSB
for
224-Bit Packet
2nd for 1st TLC59711
LSB
Timing clock for 1st display.
Timing clock for 1st display and
2nd display data write.
Low
256 ´ 224-Bit Packet for
256th TLC59711
Low
224 Shift Clocks
224 Shift Clocks
224 ´ 256 = 57344 Clocks
8192
Shift Clocks
57344 (256 ´ 224)
Shift Clocks
65536 Clocks
Shift Clock
for 2nd Display
65536 Clocks
OUTXn
OFF
OUTXn is controlled via the PWM synchronized
with SCKI for 1st dis playperiod.
OFF
2nd Display
Period
The time is 8 periods between the last SCLK rising edge and the second to last SCLK rising edge.
The wait time changes between 2.74 ms and 666 ns, depending on the period of the shift clock.
Figure 35. Data Packet and Display Start/Update Timing 3
(External Clock Mode with 256 Cascaded Devices)
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59711
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