TLC59711 Datasheet, PDF (20/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
SBVS181 – OCTOBER 2011
www.ti.com
REGISTER AND DATA LATCH CONFIGURATION
The TLC59711 has a 224-bit shift register and a 218-bit data latch that set grayscale (GS) data, global
brightness control (BC), and function control (FC) data into the device. When the internal latch pulse is generated
and the data of the six MSBs in the shift register are 25h, the 218 following data bits in the shift register are
copied into the 218-bit data latch. If the data of the six MSBs is not 25h, the 218 data bits are not copied into the
218-bit data latch. The data in the data latch are used for GS, BC, and FC functions. Figure 23 shows the shift
register and the data latch configuration.
224-Bit Shift Register
SDTO
MSB
Write
Write
Write
Write
Write
Write
¼ Command
Command Data
Data
Data
Data
¼
Bit 5
Bit 0
Bit 217 Bit 216 Bit 215 Bit 214
223
218
217
216
215
214
Write
Data
Bit 3
3
Write
Data
Bit 2
2
Write
Data
Bit 1
1
LSB
Write
Data
Bit 0
0
SDTI
SCKI
218
6
218-Bit Data Latch
6-Bit Write
Command
Decoder
MSB
OUT
TMG
217
EXT
GCK
216
TMG
RST
215
DSP
RPT
214
LSB
¼
OUTR0 OUTR0 OUTR0 OUTR0
Bit 3
Bit 2
Bit 1
Bit 0
3
2
1
0
Internal
Latch Pulse
Write Command = 25h (100101b)
26
192
To the three groups of 7-bit BC,
PWM timing control, GS clock counter,
and clock select circuit.
To GS timing control circuit.
The internal latch pulse is generated
after eight periods between the last
2 SCKI rising edges with no input.
Figure 23. Common Shift Register and Control Data Latch Configuration
224-Bit Shift Register
The 224-bit shift register is used to input data from the SDTI pin with the SCKI clock into the TLC59711. The
shifted data in this register is used for GS, BC, and FC. The six MSBs are used for the write command. The LSB
of the register is connected to the SDTI pin and the MSB is connected to the SDTO pin. On each SCKI rising
edge, the data on SDTI are shifted into the register LSB and all 224 bits are shifted towards the MSB. The
register MSB is always connected to SDTO. When the device is powered up, the data in the 224-bit shift register
is not set to any default value.
218-Bit Data Latch
The 218-bit data latch is used to latch the GS, BC, and FC data. The 218 LSBs in the 244-bit shift register are
copied to the data latch when the internal latch pulse is generated with the 6-bit write command, 25h (100101b).
When the device is powered up, the data in the latch are not reset except for BLANK (bit 213) which is set to '1'
to force all outputs off. Therefore, GS, BC, and FC data must be set to the proper values before BLANK is set to
'0'. The 218-bit data latch configuration is shown in Figure 24 and the data bit assignment is shown in Table 5.
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