TLC59711 Datasheet, PDF (21/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
www.ti.com
SBVS181 – OCTOBER 2011
218-Bit Data Latch
MSB
217
OUTTMG
1=
Rising Edge
216
EXTCLK
1=
External
215
TMGRST
1=
Reset
214
DSPRPT
1=
Repeat
Function Control Data (5 Bits)
5
213
BLANK
1=
Blank
From LSB-side of 224-bit shift register.
218
212-206 205-199 198-192
BC Data
Bits 6-0
for BLUE
BC Data
Bits 6-0
for GREEN
BC Data
Bits 6-0
for RED
BC Data for OUTRn/Gn/Bn
(7 Bits ´ 3 = 21 Bits)
21
191
176
OUTB3
¼
OUTB3
Bit 15
Bit 0
GS Data for OUTB3
(16 Bits)
31
16
¼
OUTG0
¼
OUTG0
Bit 15
Bit 0
GS Data for OUTG0
(16 Bits)
192
LSB
15
0
OUTR0
¼
OUTR0
Bit 15
Bit 0
GS Data for OUTR0
(16 Bits)
To function control (FC) circuit.
To global brightness control (BC) circuit.
To grayscale timing control (GS) circuit.
Figure 24. 218-Bit Data Latch Configuration
BIT NUMBER
15-0
31-16
47-32
63-48
79-64
95-80
111-96
127-112
143-128
159-144
175-160
191-176
198-192
205-199
212-206
213
214
215
216
217
BIT NAME
GSR0
GSG0
GSB0
GSR1
GSG1
GSB1
GSR2
GSG2
GSB2
GSR3
GSG3
GSB3
BCR
BCG
BCB
BLANK
DSPRPT
TMGRST
EXTGCK
OUTTMG
Table 5. Data Latch Bit Assignment
CONTROLLED CHANNEL/FUNCTIONS
GS data bits 15 to 0 for OUTR0
GS data bits 15 to 0 for OUTG0
GS data bits 15 to 0 for OUTB0
GS data bits 15 to 0 for OUTR1
GS data bits 15 to 0 for OUTG1
GS data bits 15 to 0 for OUTB1
GS data bits 15 to 0 for OUTR2
GS data bits 15 to 0 for OUTG2
GS data bits 15 to 0 for OUTB2
GS data bits 15 to 0 for OUTR3
GS data bits 15 to 0 for OUTG3
GS data bits 15 to 0 for OUTB3
BC data bits 6 to 0 for OUTR0-3
BC data bits 6 to 0 for OUTG0-3
BC data bits 6 to 0 for OUTB0-3
Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank).
When this bit is '0', all constant-current outputs (OUTR0-OUTB3) are controlled by the GS PWM timing
controller. When this bit is '1', all constant-current outputs are forced off. The GS counter is reset to '0',
and the GS PWM timing controller is initialized. When the IC is powered on, this bit is set to '1'.
Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is '0', the auto repeat function is disabled. Each constant-current output is only turned on
once, according the GS data after BLANK is set to '0' or after the internal latch pulse is generated with
the TMGRST bit set to '1'. When this bit is '1', each output turns on and off according to the GS data
every 65536 GS reference clocks.
Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is '1', the GS counter is reset to '0' and all constant-current outputs are forced off when
the internal latch pulse is generated for data latching. This function is the same when BLANK is set to
'0'. Therefore, BLANK does not need to be controlled by an external controller when this mode is
enabled. When this bit is '0', the GS counter is not reset and no output is forced off even if the internal
latch pulse is generated.
GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock).
When this bit is '1', PWM timing refers to the SCKI clock. When this bit is '0', PWM timing refers to the
internal oscillator clock.
GS reference clock edge select bit for OUTXn on-off timing contro in FC datal (0 = falling edge, 1 =
rising edge).
When this bit is '1', OUTXn are turned on or off at the rising edge of the selected GS reference clock.
When this bit is '0', OUTXn are turned on or off at the falling edge of the selected clock.
Copyright © 2011, Texas Instruments Incorporated
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