TLC59711 Datasheet, PDF (23/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
www.ti.com
SBVS181 – OCTOBER 2011
DISPLAY TIMING RESET FUNCTION
This function allows the display timing to be initialized using the internal latch pulse, as shown in Figure 27. This
function can be enabled or disabled by TMGRST (bit 215) in the data latch. When the TMGRST bit is '1', the GS
counter is reset to '0' and all outputs are forced off when the internal latch pulse is generated. This function is the
same when the BLANK bit changes (such as from '0' to '1' and from '1' to '0'). Therefore, the BLANK bit does not
need to be controlled from an external controller to restart the PWM control from the next GS reference clock
rising edge. When this bit is '0', the GS counter is not reset and no output is forced off even if the internal latch
pulse is generated. Figure 27 shows the display timing reset operation.
BLANK Bit
in Data Latch
(Internal)
0 = No BLANK.
TMGRST Bit
in Data Latch
(Internal)
EXTCLK Bit
in Data Latch
(Internal)
OUTTMG Bit
in Data Latch
(Internal)
1 = Display timing reset function is enabled.
1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
SCKI
Internal Latch Pulse
(Internal)
N-4 N-3 N-2 N-1 N
Period A
8x Period A
8x or greater internal
1
2
3¼
clock period
(1.34 ms, min).
GS Counter
for PWM Control
(Internal)
OFF
OUTXn
ON
M-4 M-3 M-2 M-1
M
When the TMGRST bit is ‘1’, the GS counter is
reset to ‘0’ at the internal latch pulse generation timing.
Also, OUTXn is forced off at the same time.
ON
0
OFF
Figure 27. Display Timing Reset Function
1
2
3
ON
OUTPUT TIMING SELECT FUNCTION
This function selects the on-off change timing of the constant-current outputs (OUTXn) set by OUTTMG (bit 217)
in the data latch. When this bit is '1', OUTXn are turned on or off at the rising edge of the selected GS reference
clock. When this bit is '0', OUTXn are turned on or off at the falling edge of the selected clock. Electromagnetic
interference (EMI) of the total system can be reduced using this bit setting. For example, when the odd number
of devices in the system have this bit set to '0' and the even number of devices in the system have this bit set to
'1', EMI is reduced because the devices change the OUTXn status at a deferent timing. Figure 28 and Figure 29
show the output switching timing when the OUTTMG bit is '1' and '0', respectively.
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