TLC59711 Datasheet, PDF (28/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
SBVS181 – OCTOBER 2011
www.ti.com
Data Write and PWM Control with External Grayscale Clock Mode
When the EXTCLK bit is '1', the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n =
0-3) as the GS reference clock. This mode is ideal for video image applications that change the display image
with high frequencies or for certain display applications that must synchronize all TLC59711s. The data and clock
timing are shown in Figure 9 and Figure 34. A writing procedure for the display data and display timing control
follows:
1. Power- up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet MSB-first for the Nth TLC59711 using the SDTI and SCKI signals. The first six
bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b);
otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK
bit must be set to '1' for the external oscillator mode. Also, the DSPRPT bit should be set to '0' so that the
PWM control is not repeated, the TMGRST bit should be set to '1' to reset the PWM control timing at the
internal latch pulse generation, and BLANK must be set to '0' to start the PWM control.
3. Write the 224-bit data for the (N – 1) TLC59711 without delay after step 2.
4. Repeat the data write sequence until all TLC59711s have data. The total shift clock count (SCKI) is 224 × N.
After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI
rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices.
5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34µs or more from step 4.
The OUTXn are turned on when the output GS data are not 0000h.
6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized
with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
7. Repeat step 2 to step 6 for the next display period.
VLED Power
Shift Data From
Controller (SDTI)
Shift Clock From
Controller (SCKI)
MSB
LSB
224-Bit Packet
for Nth TLC59711
for
N-1st
MSB
224 Shift Clocks
MSB
LSB
for
224-Bit Packet
2nd
for 1st TLC59711
LSB
224 Shift Clocks
The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
Low
MSB
224-Bit Packet
for Nth TLC59711
65536 Shift Clocks as GS Clock
224 Shift
Clocks
Latch Pulse
(Internal)
OUTXn
OUTXn is controlled via the PWM
synchronized with SCKI.
The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.
Figure 34. Data Packet and Display Start/Update Timing 2 (External Clock Mode)
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