TLC59711 Datasheet, PDF (27/36 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum PWM, RGB, LED Driver

TLC59711
www.ti.com
SBVS181 – OCTOBER 2011
Data Write and PWM Control with Internal Grayscale Clock Mode
When the EXTCLK bit is '0', the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n =
0-3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at
low frequencies. The data and clock timing is shown in Figure 9 and Figure 33. A writing procedure for the
function setting and display control follows:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC59711 using the SDTI and SCKI signals.
The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h
(100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch.
The EXTCLK bit must be set to '0' for the internal oscillator mode. Also, the DSPRPT bit should be set to '1'
to repeat the PWM timing control and BLANK set to '0' to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC59711 without delay after step 2.
4. Repeat the data write sequence until all TLC59711s have data. The total shift clock count (SCKI) is now 224
× N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last
SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.
VLED Power
Shift Data From
Controller (SDTI)
Shift Clock From
Controller (SCKI)
MSB
LSB
MSB
224-Bit Packet
for Nth TLC59711
224-Bit Packet
for N-1st TLC59711
for
N-2’th
MSB
LSB
224 Shift Clocks
224 Shift Clocks
The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
LSB
MSB
LSB
for
224-Bit Packet
3’rd
for 2nd TLC59711
224-Bit Packet
for 1st TLC59711
Next
Data
MSB
LSB
MSB
224 Shift Clocks
224 Shift Clocks
Next
Shift Clock
Latch Pulse
(Internal)
OUTXn
PWM Control Start
or data updated
The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.
Figure 33. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59711
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