TLC320AD91 Datasheet, PDF (24/43 Pages) Texas Instruments – Stereo Audio Codec

Table 2–10. Left Record Select Control Register Definitions
SL2 – SL0
000
001
010
011
100
101
110
111
LEFT RECORD SOURCE
MIC_IN
CDL
VIDEO_IN_L
AUXL
LINEL
Stereo Mix (L)
Mono Mix (L)
PHONE
2.3.6 Record Gain Register (Index 1Ch)
The Record Gain register is for the stereo input. Each step corresponds to 1.5 dB with 22.5 dB corresponding
to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel is set
to maximum attenuation.
The default value of this register is 8000h which represents 0-dB gain with mute on. The Record Gain
register definitions are listed in Tables 2–11.
Table 2–11. Record Gain Register Definitions
MUTE Gx3 – Gx0
FUNCTION
1111 22.5-dB Gain
0
...
...
0000 0-dB Gain
1
xxxx Maximum attenuation (mute)
2.3.7 General-Purpose Register (Index 20h)
The General-Purpose register is used to control several miscellaneous functions of the TLC320AD91C:
microphone output select, microphone select, and loopback.
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
The default value of this register is 0000h. The General-Purpose register definitions are listed in Table 2–12.
Table 2–12. General-Purpose Register Definitions
BIT
MIX
MS
LPBK
FUNCTION
Mono select. 0 = Mix, 1 = Mic
Mic select. 0 = MIC1, 1 = MIC2
ADC/DAC loopback mode.
0: Off
1: Enables loopback of the ADC output to the DAC input without involving the AC-Link thus allowing
for full system performance measurements.
2.3.8 Power-Down Control/Status Register (Index 26h)
The Power-Down Control/Status register is a read/write register used to program power-down states and
monitor subsystem readiness. The lower half of this register is read-only status with a one indicating that
the subsection is ready. Ready is defined as the subsection that is able to perform in its nominal state. When
this register is written, the bit values received on the AC-link have no effect on read-only bits 0–7.
When the AC-Link Codec Ready indicator bit (SDATIN, slot 0, bit 15) is a one, the AC-link and
TLC320AD91C control and status registers are in a fully operational state. The digital controller must further
probe this Power-Down Control/Status register to determine which subsections, if any, are ready. The
Power-Down Control/Status register bits D0–D3 definitions are listed in Table 2–13.
2–12