TLC320AD91 Datasheet, PDF (19/43 Pages) Texas Instruments – Stereo Audio Codec

2.2.4 AC-Link Low-Power Mode
The TLC320AD91C implementation of the AC-Link can be placed in a low-power mode (see Section 2.7,
Power-Down Management). When the TLC320AD91C Power Down register (26h) is programmed to the
appropriate value, both BITCLK and SDATIN are brought to and held at low-voltage logic levels.
As shown in Figure 2–4, BITCLK and SDATIN are transmitted low immediately following the decode of the
write to the Power Down Register (26h) with PR4. When the digital controller driver is at the point where it
is ready to program the TLC320AD91C into its low-power mode, slots one and two are assumed to be the
only valid stream in the audio output frame. (At this point, all sources of audio input are assumed to have
also been neutralized.)
SYNC
BITCLK
(Not To Scale)
SDOUT
SDATIN
Slot 12
Prev. Frame
Slot 12
Prev. Frame
TAG
TAG
Write To
00×26
Data
ÎÎÎÎÎÎÎÎ _PR4
Figure 2–4. TLC320AD91C Power-Down Mode Timing
The digital controller must also drive SYNC and SDOUT low after programming the TLC320AD91C to this
low-power halted mode.
Once the TLC320AD91C has been instructed to halt BITCLK, a special wake-up protocol must be used to
bring the AC-Link to the active mode since normal audio output and input frames cannot be communicated
in the absence of BITCLK.
The AC-Link can be made active again by means of a warm reset or a cold reset. See Section 2.5, Resetting
the TLC320AD91C for details on the procedure. In summary, a warm reset is accomplished by asserting
SYNC in the absence of BITCLK. The TLC320AD91C responds according to the protocol. A warm reset
retains the values programmed into the registers. A cold reset is accomplished by asserting RESET. Again,
the TLC320AD91C responds according to the protocol. A cold reset sets all register values to their default
values. Note that for both cases of a reset, the signals RESET and SYNC are treated as asynchronous
inputs.
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