TLC320AD91 Datasheet, PDF (17/43 Pages) Texas Instruments – Stereo Audio Codec

2.2.3 Frame Contents
The SDOUT frame contents are listed in Table 2–2.
Table 2–2. SDOUT Frame Contents (Driven by Audio Controller)
SLOT SLOT NAME
0 TAG
1 Command Address
2 Command Data
3 PCM Left Playback
PCM Right
4 _Playback
5–12 Reserved
BIT
POSITION
NAME
15
Valid Frame
14
Slot 1 Valid
13–3
2–0
19
Slot x Valid
Zero Pad
Read/Write
18–12
Register
Index
11–0 Zero Pad
19–4
Register
Data
3–0
Zero Pad
19–4 PCM Data
3–0
Zero Pad
19–4 PCM Data
3–0
Zero Pad
Zero Pad
DESCRIPTION
0: Indicates no valid data is in this frame
1: There is at least one TDM slot containing valid data in
the frame.
0: Indicates no data is available in the first time slot of the
data phase. Slot one must be zero-padded.
1: Valid data is available in the first time slot.
0: No valid data is in slot x of the data phase. The
corresponding slot must be zero-padded.
1: Valid data is in slot x
Reserved. Must be zeroes.
0: Write to the addressed register
1: Read from the addressed register
These seven bits are used to access the control registers.
Only the even numbers are used. A total of 64 registers
are defined. Odd numbered register accesses map to the
preceding even boundary.
Reserved. Must be zeroes.
If the current command operation is a write (see bit 19 of
slot one) then these bits contain the data to be written.
These bits must be zero-padded if the current operation
is a read.
Reserved. Must be zeroes.
18-bit audio data. If the resolution is less than 18 bits, then
the data must be right-justified and the LSBs must be
zero-padded.
These bits must be zeroes.
18-bit audio data. If the resolution is less than 18 bits, then
the data must be right-justified and the LSBs must be
zero-padded.
These bits must be zeroes.
Reserved. These bits must be zeroes. Note that slot five
is the optional modem line codec.
2–5