TLC320AD91 Datasheet, PDF (15/43 Pages) Texas Instruments – Stereo Audio Codec

The AC-Link signal definitions are listed in Table 2–1.
Table 2–1. AC-Link Signal Definitions
SIGNAL
SYNC
BITCLK
SDOUT
SDATIN
RESET
SOURCE
Controller
Codec
Controller
Codec
Controller
DESCRIPTION
Marks the beginning of each frame. Sourced by the controller. Occurs at a fixed
rate of 48 kHz unless in power-down mode. Synchronous to BITCLK. Width of 18
bits. Defines the TAG phase.
Sourced by TLC320AD91C. Fixed rate of 12.288 MHz. One bit is transmitted on
every rising edge. One bit is captured on every falling edge.
Serial bit stream sent from the controller to the codec. Data and control are
transmitted by the controller.
Serial bit stream sent from the codec to the controller. Data and control are
transmitted by the TLC320AD91C.
Reset signal used to bring the TLC320AD91C out of power-down mode. Defines
the cold TLC320AD91C reset.
2.2.2 Protocol
The TLC320AD91C protocol includes the following:
• The AC-Link is a TDM serial interface consisting of 256 bits/frame.
• Each frame is divided into two sections: A TAG phase of 18 bits, and a DATA phase of 240 bits.
• The DATA phase is divided into 12 time slots with each time slot consisting of 20 bits.
• Data is bidirectional with SDOUT transmitted by the controller, and SDATIN transmitted by the
codec.
BITCLK
SYNC
SDOUT
SDATIN
Valid ^{Slot Slot}
Slot 0 0 0 19
0 19
0
12
12
Cdc Slot Slot
Slot 0 0 0 19
0 19
0
Rdy 1 2
12
19
0
19
0
TAG Phase
Slot 1
Slot 2
Slot 12
Figure 2–3. AC-Link Protocol
2.2.2.1 Zero-Padding
The TLC320AD91C uses zero-padding which is defined as the following:
• Reserved time-slots are filled with zeroes.
• Unused bits within a time-slot must be filled with zeroes (e.g., 18-bit converter in a 20-bit time
slot). This operation must be performed by the source (i.e., the controller for SDOUT, the
TLC320AD91C for SDATIN).
• Time slots tagged as invalid must be filled with zeroes.
2–3