TLC320AD91 Datasheet, PDF (18/43 Pages) Texas Instruments – Stereo Audio Codec

The SDATIN frame contents are listed in Table 2–3.
SLOT
0
1
2
3
4
5–12
SLOT NAME
TAG
Status Address
Status Data
PCM Left Record
PCM Right Record
Reserved
Table 2–3. SDATIN Frame Contents
BIT
POSITION
NAME
DESCRIPTION
0: Indicates the TLC320AD91C codec is not ready.
1: Indicates the TLC320AD91C control and status
15
Codec Ready _{registers are available and the AC-Link is operational.}
The audio controller can then probe further to
determine when other sections become available.
0: Indicates no data is available in the first time slot of
the data phase. Slot one must be zero-padded.
14
Slot 1 Valid
1: Valid data is available in the first time slot if the
codec is ready.
13–3
Slot x Valid
0: No valid data is in slot x of the data phase. The
corresponding slot must be zero-padded.
1: Valid data is in slot x if the codec is ready.
2–0
Zero Pad
Reserved. Must be zeroes.
19
Zero Pad
Reserved. Must be zero.
18–12
Register Index
These seven bits are used to echo the control register
address. The data appears in the next slot (slot two).
These bits must be zero-padded if this slot is flagged
invalid during the TAG phase.
11–0 Zero Pad
Reserved. Must be zeroes.
19–4
Register Data
Contents of the register addressed by slot one (status
address). These bits must be zero-padded if this slot
is flagged invalid during the TAG phase.
3–0
Zero Pad
These bits are zeroes.
19–4 PCM Data
18-bit audio data.
3–0
Zero Pad
These bits must be zeroes.
19–4 PCM Data
18-bit audio data.
3–0
Zero Pad
These bits are zeroes.
Zero Pad
Reserved. These bits must be zeroes. Note that slot
five is the optional modem line codec, and slot six is
the optional microphone ADC record data.
2–6