TLC320AD91 Datasheet, PDF (21/43 Pages) Texas Instruments – Stereo Audio Codec

Table 2–4. TLC320AD91C Register Definitions (Continued)
INDEX NAME D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
D0 DEFAULT
Record
1Ah Select
0
0
0
0
0 SL2 SL1 SL0 0
0
0
0
0 SR2 SR1 SR0 0000h
Control
1Ch
Record
Gain
Mute 0
0
0 GL3 GL2 GL1 GL0 0
0
0
0 GR3 GR2 GR1 GR0 8000h
1Eh^†
Record
Gain Mic
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
20h
General
Purpose
0 ST 3D 1D
0
0 MIX MS LPBK 0
0
0
0
0
0
0
0000h
22h^†
3D
Control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
Modem
24h^† Rate (Not 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
Used)
Power-
26h
Down
Control/
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
0
0
0 MDM REF ANL DAC ADC
na
Status
28h–
59h
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5Ah– Vendor
7Ah Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
7Ch
Vendor
ID1
F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5
S4 S3 S2 S1 S0
5458h
7Eh
Vendor
ID2
T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0000h
† _{Optional AC‘97 registers whose functionality are not implemented on the TLC320AD91C. These registers can be written to, but reads always return zeroes.}
‡ _{Special function volume settings. If bit is set, then the 5 volume bits implemented are set to all ones.}
NOTE: All registers and all bits in all registers must have read back capabilities (be readable) to facilitate testing.