TLC320AD91 Datasheet, PDF (16/43 Pages) Texas Instruments – Stereo Audio Codec

2.2.2.2 SYNC
The TLC320AD91C SYNC signal includes the following characteristics:
• SYNC is driven by the controller.
• SYNC is derived by dividing down the BITCLK signal (BITCLK is an input to the controller).
• SYNC is high for 18 BITCLKs at the beginning of each frame. These 18 BITCLKs (bits) define
the TAG phase. The TAG phase defines the beginning of a frame.
• The TLC320AD91C synchronizes data conversion with the rising edge of SYNC.
• SYNC remains low for the next 240 BITCLKs. These 240 BITCLKs (bits) define the DATA phase.
• SYNC is sampled by TLC320AD91C at the falling edge of BITCLK.
• SYNC transition edges are on the rising edge of BITCLK.
• The controller must hold SYNC low during a TLC320AD91C power-down halted state.
2.2.2.3 BITCLK
The TLC320AD91C BITCLK signal includes the following characteristics:
 • BITCLK is fixed at 12.288 MHz (256 sampling rate). The sampling rate is fixed at 48 kHz.
• BITCLK is sourced by the TLC320AD91C.
• BITCLK goes low and remains low when a write to register 26h with PR4 is detected (power-down
state).
• BITCLK becomes active from a power-down state in response to a cold or warm TLC320AD91C
reset condition.
2.2.2.4 SDOUT
The TLC320AD91C SDOUT signal includes the following characteristics:
• SDOUT is driven by the controller.
• SDOUT transitions on the rising edge of BITCLK.
• SDOUT is captured by the TLC320AD91C on the falling edge of BITCLK.
• The controller must hold SDOUT low during an TLC320AD91C power-down halted state.
2.2.2.5 SDATIN
The TLC320AD91C SDATIN signal includes the following characteristics:
• SDATIN is driven by the TLC320AD91C.
• SDATIN transitions on the rising edge of BITCLK.
• SDATIN is captured by the controller on the falling edge of BITCLK.
• SDATIN goes low and remains low when a write to register 26h with PR4 is detected (power-down
state).
• SDATIN becomes active from a power-down state in response to a cold or warm TLC320AD91C
reset condition.
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