BQ26501_16 Datasheet, PDF (24/33 Pages) Texas Instruments – HANDHELD APPLICATIONS

bq26501
Not Recommended For New Designs
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SLUS586B − OCTOBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
COMMUNICATING WITH THE bq26501
The bq26501 includes a single-wire HDQ serial data interface. Host processors, configured for either polled or
interrupt processing, can use the interface to access various bq26501 registers. The HDQ pin is an open drain
device, which requires an external pull-up resistor. The interface uses a command-based protocol, where the
host processor sends a command byte to the bq26501. The command directs the bq26501 to either store the
next eight bits of data received to a register specified by the command byte, or to output the eight bits of data
from a register specified by the command byte.
The communication protocol is asynchronous return-to-one and is referenced to V_SS. Command and data bytes
consist of a stream of eight bits that have a maximum transmission rate of 5 Kbits/s. The least-significant bit
of a command or data byte is transmitted first. Data input from the bq26501 may be sampled using the
pulse-width capture timers available on some microcontrollers. A UART can also be configured to communicate
with the bq26501.
If a communication time-out occurs (for example, if the host waits longer than t_(RSPS) for the bq26501 to
respond) or if this is the first access command, then a BREAK should be sent by the host. The host may then
resend the command. The bq26501 detects a BREAK when the HDQ pin is driven to a logic-low state for a time
t_(B) or greater when the bus is free. If the host sends a BREAK when the bq26501 is transmitting a bit, it is
possible that the BREAK would be ignored. Best practice is to hold all BREAK transmissions for twice the
minimum time listed in the HDQ specification table. The HDQ pin then returns to its normal ready-high logic state
for a time t_(BR).The bq26501 is then ready for a command from the host processor.
The return-to-one data-bit frame consists of three distinct sections:
1. The first section starts the transmission by either the host or the bq26501 taking the HDQ pin to a logic-low
state for a period equal to t_(HW1) or t_(DW1).
2. The next section is the actual data transmission, where the data should be valid for t_(HW0)− t_(HW1) or t_(DW0)−
t_(DW1).
3. The final section stops the transmission by returning the HDQ pin to a logic-high state and holding it high
until the time from bit start to bit end is equal to t_(CYCH) or t_(CYCD).
The HDQ line may remain high for an indefinite period of time between each bit of address or between each
bit of data on a write cycle. After the last bit of address is sent on a read cycle, the bq26501 starts outputting
the data after t_(RSPS) with timing as specified. The serial communication timing specification and illustration
sections give the timings for data and break communication. Communication with the bq26501 always occurs
with the least-significant bit being transmitted first.
Plugging in the battery pack may be seen as the start of a communication due to contact bounce. It is
recommended that each communication or string of communications be preceded by a break to reset the HDQ
engine.
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