BQ26501_16 Datasheet, PDF (19/33 Pages) Texas Instruments – HANDHELD APPLICATIONS

Not Recommended For New Designs
bq26501
ą
SLUS586B − OCTOBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
Identification Byte #3 (ID3) − Address 0x7D
This register may be programmed to any desired value.The contents do not affect the operation of the bq26501.
Discharge Rate Compensation Constants (DCOMP) or ID2 − Address 0x7E
This register is used to set the compensation coefficients for discharge rate. These coefficients are applied to
the nominal available charge (NAC) to more accurately predict capacity at high discharge rates.
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DCGN[5] DCGN[4] DCGN[3] DCGN[2] DCGN[1] DCGN[0] DCOFF[1] DCOFF[0]
MODE
REGISTER
DCGN[5]
DCGN[4]
DCGN[3]
DCGN[2]
DCGN[1]
DCGN[0]
DCOFF[1]
DCOFF[0]
DESCRIPTION
Discharge rate compensation gain. Used to set the slope of the discharge capacity compensation as a
percentage of discharge current. The gain factor adjustment is in increments of 0.39% of discharge current in
excess of the DCOFF value. The equation for programming the value is:
DCGN[5:0] = 2.56 × design discharge compensation gain %
These bits set the discharge threshold of compensating the nominal available charge for discharge rate. The
threshold is set as shown in Table 4.
Table 4. Discharge Rate Compensation Thresholds
DCOFF[1]
0
0
1
1
DCOFF[0]
0
1
0
1
DCOFF
THRESHOLD
0
LMD/2
LMD/4
LMD/8
Discharge compensation, DCMP, is computed from these coefficients as follows:
DCMP + ^DCGN
(AI * DCOFF)
256
(9)
where DCMP is restricted to ≥ 0. AI is the average discharge current. The CACD register then takes on the value:
CACD + NAC * (DCMP * DCMPADJ), if DCMP u DCMPADJ or
(10)
CACD + NAC, if DCMP v DCMPADJ
(11)
where DCMPADJ is the value of DCMP at a previous EDV1 detection. This allows the compensation for CACD
to adapt as the LMD value is learned.
If PKCFG[1]=1, the device assumes a fixed value of 0x42 for DCOMP, giving a discharge rate compensation
gain of 6.25% with a compensation threshold of C/4. This frees the EEPROM location of 0x7E for a user-defined
identification byte, ID2.
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