BQ26501_16 Datasheet, PDF (18/33 Pages) Texas Instruments – HANDHELD APPLICATIONS

bq26501
Not Recommended For New Designs
ą
SLUS586B − OCTOBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
Pack Configuration (PKCFG) − Address 0x7C
BIT 7
BIT 6
BIT 5
NAME
GPIEN
QV1
QV0
BIT 4
RSVD
BIT 3
RSVD
BIT 2
RSVD
BIT 1
DCFIX
BIT 0
TCFIX
PKCFG
REGISTER
GPIEN
QV1
QV2
RSVD
DCFIX
TCFIX
DESCRIPTION
Allows the pack manufacturer to set the state of the GPIO pin on initial power up. If the bit is “0”, the GPIEN bit is
cleared on reset and the GPIO pin acts as a high impedance output. If the bit is “1”, the GPIEN bit is set on reset
and the GPIO pin acts as an input. The state of the GPIO pin can then be read through the GPSTAT bit in the
MODE register.
These bits set the end voltage for charge termination. The terminating voltage is set as shown in Table 3.
No function.
Fixed discharge compensation. Normal discharge rate compensation (DCOMP register) is used if this bit is set to
“0”. If this bit is set to “1”, the device assumes a fixed value of 0x42 for DCOMP, giving a discharge rate
compensation gain of 6.25% with a compensation threshold of C/4. Setting the bit to “1” frees the EEPROM
location of 0x7E for use as a programmable identification byte.
Fixed temperature compensation. Normal temperature compensation (TCOMP register) is used if this bit is set to
“0”. If this bit is set to “1”, the device assumes a fixed value of 0x7C for TCOMP, giving a temperature
compensation gain of 0.68% of Design Capacity/°C with an offset of 12°C. Setting this bit to “1” frees the
EEPROM location of 0x7F for use as a programmable identification byte.
Table 3. Charge Termination Voltage Settings
QV1
0
0
1
1
QV2
0
1
0
1
VOLTAGE (mV)
3968
4016
4064
4112
18
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