GC5328 Datasheet, PDF (23/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
www.ti.com
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
LVDS SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.
N means the number of differential pairs used to transmit data from one ADC, and M means the number of bits sent serially
down each LVDS pair. Thus, 8x2 means eight LVDS pairs, each containing 2 bits of information sent serially. NOTE: The
ADC clock rate must match the DPDClock rate for real feedback.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
16x1 SDR LVDS MODE ex. ADS5444
f_CLK(ADC)
ADC interface clock frequency
t_su(ADC[#]P)
Input data setup time before CLK↑
t_h(ADC[#]P)
Input data hold time after CLK↑
8x2 DDR LVDS MODE ex. ADS5545, ADS6149
f_CLK(ADCA)
t_{su(ADCA[#/2]P)}
t_{h(ADCA[#/2]P)}
f_CLK(ADCB)
t_{su(ADCB[#/2]P)}
t_{h(ADCB[#/2]P)}
ADCA interface clock frequency
Input data setup time before CLK↑↓
Input data hold time after CLK↑↓
ADCB interface clock frequency
Input data setup time before CLK↑↓
Input data hold time after CLK↑↓
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
200 MHz
300
ps
600
ps
See ⁽¹⁾
200 MHz
See^{(1) (3)}. For port A
430
ps
See^{(1) (3)}. For port A
260
ps
See ⁽¹⁾
200 MHz
See^{(1) (4)}. For port B
800
ps
See^{(1) (4)}. For port B
400
ps
(1) Specifications are limited by GC5328 performance and may exceed the example ADC capabilities for the given interface.
(2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing
(VOD = 0).
(3) Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (VOD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing
(VOD = 0).
(4) Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (VOD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing
(VOD = 0).
CLK
CLKC
1/f_CLK(ADC)
ADC[15:0]P
ADC[15:0]N
t_su(ADC[#]P)
t_h(ADC[#]P)
T0291-01
Figure 18. LVDS Timing Specification (16x1 SDR LVDS)
CLK
CLKC
1/f_CLK(ADCx)
ADC[# bits/2]P
ADC[# bits/2]N
t_{su(ADCx[#/2]P)}
Even Bits
Odd Bits
t=N
t_{h(ADCx[#/2]P)}
t=N+1
Even Bits
Odd Bits
Figure 19. LVDS Timing Specification (8x2 DDR LVDS)
T0293-01
Copyright © 2009, Texas Instruments Incorporated
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