GC5328 Datasheet, PDF(12/27 Page) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

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GC5328 Datasheet, PDF (12/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

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GC5328

SLWS218A â OCTOBER 2009 â REVISED OCTOBER 2009

www.ti.com

PIN FUNCTIONS (continued)

NAME

NO.

I/O

DESCRIPTION

BB[9:0]

C18, B18, A18, D19, C19, B19, A19, C20, B20, A20

I Baseband input signal

BBCLK

C16

I Baseband input clock

BBFR

B16

I Baseband frame for sample and channel timing

MISCELLANEOUS

RESETB

I Chip reset (active-low)

TESTMODE

AB21

I Tie to GND

SYNCA

C15

I Programmable general-purpose sync

SYNCB

B15

I Programmable general-purpose sync

SYNCC

A15

I Programmable general-purpose sync

SYNCD

AA5

I DPD-purpose sync

SYNCDC

AB5

I Complementary DPD-purpose sync

SYNCOUT

D15

O Programmable general-purpose output sync

DPDCLK

I Clock to DPD

DPDCLKC

I Complementary clock to DPD

JTAG INTERFACE

TCK

AB19

I JTAG clock

TDI

AA19

I JTAG data in

TDO

AB20

O JTAG data out

TRSTB

AA18

I JTAG reset (active-low)

TMS

AB18

I JTAG mode select

SIGNAL INTERFACE (Tx-DAC, FB-ADC, see next section for Data Converter Connections)

TX[37:30]

W17, Y17, AA17, AB17, W16, Y16, AA16, AB16

O Transmit to DAC(s)

TX[29:20]

W15, Y15, AA15, AB15, W14, Y14, AA14, AB14, AA13,

AB13

O Transmit to DAC(s)

TX[19:10]

AA12, AB12, AB11, AA11, Y11, W11, AB10, AA10, Y10,

W10

O Transmit to DAC(s)

TX[9:0]

AB9, AA9, Y9, W9, AB8, AA8, Y8, W8, AB7, AA7

O Transmit to DAC(s)

FB[35:30]

B13, A13, D13, C13, B12, A12

I Feedback from ADC(s)

FB[29:20]

D12, C12, A11, B11, A10, B10, C10, D10, A9, B9

I Feedback from ADC(s)

FB[19:10]

C9, D9, A8, B8, A7, B7, C7, D7, A6, B6

I Feedback from ADC(s)

FB[9:0]

A5, B5, C5, D5, B4, A4, D4, C4, B3, A3

I Feedback from ADC(s)

MFIO[33:0]

V1, U3, U2, U1

I/O Multifunction input-output interface

MFIO[29:20]

T3, T2 T1, R2, R1, P3, P2, P1, N3, N2

I/O Multifunction input-output interface

MFIO[19:10]

N1, M3, M2, M1, L2, L1, K3, K2, K1, J3

I/O Multifunction input-output interface

MFIO[9:0]

J2, J1, H2, H1, G3, G2, F2, F1, D3, C3

I/O Multifunction input-output interface

SPECIAL POWER-SUPPLY REQUIREMENTS FOR VDDA1, VSSA1, VDDA2, VSSA2

The two PLLs require an analog supply. Each pair (VDDA1, VSSA1) requires a separate filter. These can be

generated by filtering the core digital supply (VDD). A representative filter is shown in Figure 8. The filters should

be located as close as reasonable to their respective pins (especially the bypass capacitors). The ferrite beads

should be series 50R (similar to Murata P/N: BLM31P500SPT; description: IND FB BLM31P500SPT 50R 1206).

In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required

range. The series resistor assures this condition is met.

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