GC5328 Datasheet, PDF (14/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
NOTE
There are special connections for shared-feedback ADCs between GC5328s. See the
GC5325 schematic diagram for the shared feedback connection to (2) GC5328.
Table 4. Single LVDS SDR ADC to FB Ports A and B
PIN NAME
PIN NUMBER
ADC[15:10]P FB2, FB4, FB6, FB8, FB10, FB12
DAC[9:0]P
FB14, FB16, FB20, FB22, FB24, FB26, FB28, FB30,
FB32, FB34
ADC[15:10]N FB3, FB5, FB7, FB9, FB11, FB13
ADC[9:0]N
FB15, FB17, FB21, FB23, FB25, FB27, FB29, FB31,
FB33, FB35
ADCCLK
FB0
ADCCLKC FB1
I/O
DESCRIPTION
I ADC positive feedback from PA output
I ADC negative feedback from PA output
I ADC negative feedback from PA output
I ADC negative feedback from PA output
I Clock from ADC
I Complementary clock from ADC
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PIN NAME
ADCA[7:0]P
ADC[9:0]P
ADCACLK
ADCACLKC
Table 5. Single LVDS DDR ADC to FB Port A (Preferred)
PIN NUMBER
FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16
FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17
FB0
FB1
I/O
DESCRIPTION
I ADC-A positive feedback from PA output
I ADC-A negative feedback from PA output
I Clock from ADC-A
I Complementary clock from ADC-A
PIN NAME
ADCB[7:0]P
ADCB[7:0]N
ADCBCLK
ADCBCLKC
Table 6. Single LVDS DDR ADC to FB Port B
PIN NUMBER
FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34
FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35
FB18
FB19
I/O
DESCRIPTION
I ADC-B positive feedback from PA output
I ADC-B negative feedback from PA output
I Clock from ADC-B
I Complementary clock from ADC-B
MPU INTERFACE GUIDELINES
The following section describes the hardware interface between the recommended microprocessor, external
memory, and the GC5328. Users may select a microprocessor that meets their specific system requirements.
Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully
supported with host control and adaptation software. Figure 7 and Figure 9 illustrate the hardware interface
between the DSP, GC5328, and SDRAM. The external memory is required to accommodate the computational
efforts of the adaptation algorithm. Although the system evaluation kit suggests dual-parallel 64-Mb/PC133
(128-Mb) memory modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are
available.
The use of an external inverter with minimal propagation delay is required for OEB of the GC5328; this device is
necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in
the TMS320C672x Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP
External Memory Interface (EMIF) user's guide (SPRU711).
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