GC5328 Datasheet, PDF (16/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
T_J
Junction temperature
See ⁽³⁾
MIN
TYP
MAX UNIT
105 °C
(3) Thermal management may be required for full-rate operation. Sustained operation at elevated temperatures reduces long-term reliability.
Lifetime calculations based on maximum junction temperature of 105°C.
THERMAL CHARACTERISTICS⁽¹⁾
PARAMETER
484 BGA AT 2.5 W
UNITS
R_θJA
R_θJMA1
R_θJC
R_θJB
Thermal resistance, junction-to-ambient (still air)
Thermal resistance, junction-to-ambient (1 m/s)
Thermal resistance, junction-to-case
Thermal resistance, junction-to-board
18
°C/W
14.3
°C/W
6.8
°C/W
8
°C/W
(1) Customer must check that heat removal is appropriate for the application to limit the junction temperature (T_J) aspecified in the
Recommended Operating Conditions. Conducting heat through the ground and power balls, or adding a heat sink and airflow, may be
needed to limit junction temperature.
ELECTRICAL CHARACTERISTICS
Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU
and JTAG interfaces over recommended operating conditions. Device is production tested at 90°C for the given specification
and characterized at –40°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
CMOS INTERFACE
V_IL
CMOS voltage input, low
V_IH
CMOS voltage input, high
V_OL
CMOS voltage output, low
I_OL = 2 mA
V_OH
CMOS voltage output, high
I_OH = –2 mA
|I_PU|
Pullup current
V_IN = 0 V
|I_IN|
Leakage current
V_IN = 0 or V_IN = V_DDSHV
DAC INTERFACE (DACP/N[15:0])
V_o(diff)
V_comm
Output differential swing
Common mode
| V_OD | = | V_OH – V_OL |⁽¹⁾
(V_OH + V_OL) / 2⁽¹⁾
LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C)
0.8 V
2
V_DDSHV
V
0.5 V
2.4
VDDSHV V
40
100
200 μA
5 μA
250
mV
1000
mV
V_I
V_I(diff)
Input voltage range
Input differential voltage,
|Vpos – Vneg|
R_IN
Input differential impedance
POWER SUPPLY
I_dyn
Core current
0 < Vi < 2000 mV
1000 mV < V_I < 1400 mV, FB[35:0] only
See ⁽²⁾
0
250
90
80
2000 mV
mV
120 Ω
1.7 A
(1) HSTL output levels measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360.
(2) 400-Mbps DAC signal, 200-Mhz DPD clock, maximum filtering, 70-Mhz BBPLL clock input
16
Submit Documentation Feedback
Product Folder Link(s): GC5328
Copyright © 2009, Texas Instruments Incorporated