GC5328 Datasheet, PDF (10/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
PIN ASSIGNMENT AND DESCRIPTIONS
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ZER Package
(Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y AA AB
22
VSS
VSS
VSS
VSS
VSS
UP UP UP UP
ADDR ADDR ADDR ADDR
RDB
UP
DATA0
VSS
UP UP
DATA3 DATA6
VPP1
UP UP
DATA9 DATA12
UP
DATA15
VSS1
VSS
VSS
VSS
21 VSS
VSS
VSS
VSS
VSS
UP UP UP
ADDR ADDR ADDR
WRB
CEB
UP
DATA1
VSS
UP
DATA4
VPP1
UP UP
DATA7 DATA10
UP
DATA13
VSS
VSS
VSS
VSS
TEST
MODE
20 BB0
BB1
BB2
VSS
VSS
UP UP UP
ADDR ADDR ADDR
VDD
SHV
OEB
UP
DATA2
VDD
SHV
UP
DATA5
VDD
SHV
UP UP UP
DATA8 DATA11 DATA14
VSS
MVV
DD2
MVV INTER-
SS2 RUPT ^TDO
VDD
VDD
19 BB3 BB4 BB5 BB6 _SHV VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD _SHV VDD VDD TDI TCK
VDD
VDD
18 BB7 BB8 BB9 BB10 VDD VDD VDD VDD VDD1 VDD _SHV VDD VDD VDD VDD VDD VDD VDD VSS _SHV TRSTB TMS
17 BB11 BB12 BB13 BB14 VDD
VDD
VDD
SHV
VDD
VDD
VDD
VDD
SHV
VDD
VDD
VDD
VDD
VDD
SHV
VDD
VDD
TX37 TX36 TX35 TX34
16 BB15 BBFR BBCLK VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD TX33 TX32 TX31 TX30
15
SYNC SYNC SYNC SYNC
C
B
A OUT
VDD
SHV
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VHST
LHV
VDD
TX29
TX28
TX27
TX26
VDD
VHST
14 VSSA1 VDDA1 VDD VSS _SHV VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS _LHV VDD TX25 TX24 TX23 TX22
VDD
VHST
DAC DAC
13 FB34 FB35 FB32 FB33 _SHV VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS _LHV VDD _{REFN REFP} TX21 TX20
VDD
VHST
12 FB30 FB31 FB28 FB29 _SHV VDD VSS VSS VSS VSS VSS1 VSS VSS VSS VSS VSS _LHV VDD VSS VSS TX19 TX18
11 FB27 FB26 VDD
VDD ^VDD VDD
SHV1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VHST
LHV
VDD
TX14
TX15
TX16
TX17
10
FB25
FB24
FB23
FB22
VDD
SHV
VDD
VSS
VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1
VSS
VHST
LHV
VDD
TX10
TX11
TX12
TX13
9
FB21
FB20
FB19
FB18
VDD
SHV
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS
VHST
LHV
VDD
TX6
TX7
TX8
TX9
ADC ADC VDD
VHST
8 FB17 FB16 _{IREF VREF SHV} VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS _LHV VDD TX2 TX3 TX4 TX5
7 FB15 FB14 FB13 FB12 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDA TX0 TX1
VDD
VDD
VDD
VDD
6 FB11
F10
VDD
VDD
VDD
VDD
SHV
VDD VDD
VDD
SHV
VDD
VDD VDD VDD
SHV
VDD
VDD
VSS
VSS
VSSA
SHV
5 FB9
FB8
FB7
FB6
VDD VDD VDD VDD VDD VDD ^VDD VDD VDD VDD VDD VDD VDD VDD ^{DPD DPD SYNC SYNC}
SHV
CLK CLKC D
DC
4 FB4
FB5
FB2
FB3
VDD
SHV
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SHV
DPD
IREF
DPD
VREF
VSS
3 FB0
FB1
MFIO MFIO
0
1
VSS
VPP
MFIO
5
VDD
SHV
MFIO MFIO
10
13
VDD
SHV
MFIO MFIO MFIO
18
21
24
VDD
SHV
MFIO MFIO
29
32
VSS
RESET
B
VSS
VSS VSS
2
VSS
VSS
VSS
VSS
VSS
MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO
3
4
7
9
12
15
17
20
23
26
28
31
VSS
VSS
VSS
VSS
VSS
1 VSS
VSS
VSS
VSS
VSS ^MFIO VPP ^{MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO} VSS
2
6
8
11
14
16
19
22
25
27
30
33
VSS
VSS
VSS
= Baseband Input
= Microprocessor Interface
= Signal Interface
= Miscellaneous
= Power and Biasing
= JTAG Interface
P0107-01
10
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