GC5328 Datasheet, PDF (18/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
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DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
f_CLK(DPD)
Duty_CLK(DPD)
t_h(SYNCD)
t_su(SYNCD)
t_{h(SYNCA, -B, -C)}
t_{su(SYNCA, -B, -C)}
Jitter_CLK(DPD) ⁽²⁾
DPD input clock frequency
DPD input clock duty cycle
Input hold time after DPDCLK↑
Input setup time after DPDCLK↑
Input hold time after DPDCLK↑
Input setup time after DPDCLK↑
Cycle-to cycle jitter
See ⁽¹⁾
See ⁽¹⁾
100
30%
0.2
0.4
2
0.4
–2.5%
(1) Controlled by design and process
(2) Jitter is based on a period of (1/(DPDClk × 2)) (for BUC Interp 1 or 2); (1/( DPDClk × 3)) (for BUC Interp 1.5 or 3).
MAX
200
70%
2.5%
UNIT
MHz
ns
ns
ns
ns
DPDCLK
DPDCLKC
SYNCDC
SYNCD
t_su(SYNCD)
t_h(SYNCD)
SYNCA
SYNCB
SYNCC
t_{su(SYNCA, -B, -C)}
t_{h(SYNCA, -B, -C)}
T0286-01
Figure 11. DPD Clock and Fast Sync Timing Specifications
18
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