GC5328 Datasheet, PDF (22/27 Pages) Texas Instruments – GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

GC5328
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
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TX SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
HSTL MODE – SDR ex. DAC5688
f_CLK(DAC)
t_d
t_ho
DAC output clock frequency
DACCLK-to-DACData delay time
DACCLK-to-DACData hold time
2-mA load⁽¹⁾
2-mA load⁽²⁾
2-mA load⁽²⁾
200 MHz
1.5 ns
1.5
ns
(1) Because the output clock is SDR, the positive edge of the clock is used to register the data at the DAC receiver. The clock rate is limited
to 200 MHz.
(2) t_d and t_ho data clock-to-data is measured during characterization.
DACCLKC
DACCLK
DAC[15:0]
I or Q
t_ho
t_d
T0448-01
Figure 16. TX Timing Specifications (HSTL – SDR)
ENVELOPE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MFIO CMOS – SDR to Envelope Modulator
f_CLK(ENV)
ENVELOPE data output clock frequency
2-mA load⁽¹⁾
t_d
ENVCLK-to-ENVData delay time
2-mA load⁽²⁾
t_ho
ENVCLK-to-ENVData hold time
2-mA load⁽²⁾
(1) Envelope output is magnitude; this is a real output at a DPDClk/2 (100-MHz) rate.
(2) t_d and t_ho data clock-to-data is measured during characterization.
MIN TYP MAX UNIT
DPDC MHz
lk/2
1.5 ns
1.5
ns
ENVCLK
ENVDATA[15:0]
t_ho
t_d
T0449-01
Figure 17. Envelope Timing (MFIO – CMOS 3.3 V)
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