LMH2832 Datasheet, PDF (22/46 Pages) Texas Instruments – LMH2832 Fully Differential, Dual, 1.1-GHz, Digital Variable-Gain Amplifier

LMH2832
SBOS709A – JULY 2016 – REVISED JULY 2016
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Programming (continued)
9.5.2 Timing Diagrams
Figure 45 and Figure 46 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 47
shows an example timing diagram for a streaming write cycle and Figure 48 shows an example timing diagram
for a streaming read cycle. Figure 49, Figure 50, Figure 51, and Figure 52 illustrate timing diagrams and
requirements for the clock, data input, data output, and chip select, respectively. See the Timing Requirements:
SPI table for SPI timing requirements.
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 45. SPI Write Bus Cycle Timing Diagram
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 46. SPI Read Bus Cycle Timing Diagram
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Addr N
Addr N+1
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 47. SPI Streaming Write Example Timing Diagram
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A6 A5 A4 A3 A2 A1 A0
Addr N
Addr N+1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 48. SPI Streaming Read Example Timing Diagram
t_PH
t_PL
SCLK
t_PL
Figure 49. SPI Clock Timing Diagram
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