LMH2832 Datasheet, PDF (21/46 Pages) Texas Instruments – LMH2832 Fully Differential, Dual, 1.1-GHz, Digital Variable-Gain Amplifier

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LMH2832
SBOS709A – JULY 2016 – REVISED JULY 2016
9.4 Device Functional Modes
9.4.1 Power-Down (PD)
The device supports power-down control using an external power-down (PDx) pin or by writing a logic high to bit
6 of SPI register 2h (see the Register Maps section). The external PDx pins are active high; when left floating,
the device defaults to an on condition resulting from the internal pulldown resistors that cause a logic low on the
PDx pins. The device PDx thresholds are noted in the Electrical Characteristics table. The device consumes
approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down
mode.
9.4.2 Gain Control
The LMH2832 gain can be controlled from 30-dB gain (0-dB attenuation) to –9-dB gain in 1-dB steps by digitally
programming the SPI register 2h; see the Register Maps section for more details.
9.5 Programming
9.5.1 Details of the Serial Interface
The LMH2832 has a set of internal registers that can be accessed by the serial interface formed by the CS
(serial interface enable), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface
read-back data) pins. Serially shifting bits into the device is enabled when CS is low. SDI serial data are latched
at every SCLK rising edge when CS is active (low). The serial data are loaded into the register at every 16th
SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are
ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form
the register address and the remaining eight bits are the register data. The interface can function with SCLK
frequencies from 25 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. A
summary of the LMH2832 SPI protocol is:
1. SPI-1.1 interface
2. Independent channel A, B attenuation programming (6-bit gain control)
3. SPI register contents are preserved in power-down mode
4. SPI-controlled power modes (3-bit control for eight options to step down the power)
5. Powered for the main 5-V power supply
6. 1.8-V logic
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