DDC264 Datasheet, PDF (22/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
SBAS368C – MAY 2006 – REVISED JULY 2011
LAYOUT
Power Supplies and Grounding
Both AVDD and DVDD should be as quiet as
possible. It is particularly important to eliminate noise
from AVDD that is non-synchronous with the DDC264
operation. Figure 34 illustrates how to supply power
to the DDC264. Each DDC264 has internal bypass
capacitors on AVDD and DVDD; therefore, the only
external bypass capacitors typically needed are 10μF
ceramic capacitors, one per PCB. It is recommended
that both the analog and digital grounds (AGND and
DGND) be connected to a single ground plane on the
PCB.
Analog
Supply
AVDD
10mF
Digital
Supply
DVDD
10mF
0.3mF
DDC264
0.1mF
AGND
DGND
Figure 34. Power-Supply Connections
Shielding Analog Signal Paths
As with any precision circuit, careful PCB layout
ensures the best performance. It is essential to make
short, direct interconnections and avoid stray wiring
capacitance—particularly at the analog input pins and
QGND. The analog input pins are high-impedance
and extremely sensitive to extraneous noise. The
QGND pin should be treated as a sensitive analog
signal and connected directly to the supply ground
with proper shielding. Leakage currents between the
PCB traces can exceed the input bias current of the
DDC264 if shielding is not implemented. Digital
signals should be kept as far as possible from the
analog input signals on the PCB.
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POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs
must be low. At the time of power-up, all of these
signals should remain low until the power supplies
have stabilized, as shown in Figure 35. The analog
supply must come up before or at the same time as
the digital supply. At this time, begin supplying the
master clock signal to the CLK pin. Wait for time t_POR,
then give a RESET pulse. After releasing RESET, the
Configuration Register must be written to. Table 11
shows the timing for the power-up sequence.
Power Supplies
RESET
t_POR
t_RST
CLK
Configuration
Serial Interface
Write to the
Configuration Register
Figure 35. DDC264 Timing Diagram at Power-Up
Table 11. Timing for DDC264 Power-Up Sequence
SYMBOL
DESCRIPTION
t_POR
Wait after power-up
until reset
MIN TYP MAX UNITS
250
ms
22
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