DDC264 Datasheet, PDF (16/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
SBAS368C – MAY 2006 – REVISED JULY 2011
DATA FORMAT
The serial output data are provided in an offset binary
code as shown in Table 4. The Format bit in the
Configuration Register selects how many bits are
used in the output word. When Format = 1, 20 bits
are used. When Format = 0, the lower four bits are
truncated so that only 16 bits are used. Note that the
LSB size is 16 times bigger when Format = 0. An
offset is included in the output to allow slightly
negative inputs (for example, from board leakages)
from clipping the reading. This offset is approximately
0.4% of the positive full-scale.
DATA RETRIEVAL
The data from the last conversion are available for
retrieval on the falling edge of DVALID (see Figure 27
and Table 5). Data are shifted out on the falling edge
of the data clock, DCLK.
www.ti.com
Make sure not to retrieve data around changes in
CONV because this change can introduce noise.
Stop activity on DCLK at least 2μs before or after a
CONV transition.
Setting the Format bit = 0 (16-bit output word)
reduces the time needed to retrieve data by 20%
because there are fewer bits to shift out. This
technique can be useful in multichannel systems
requiring only 16 bits of resolution.
Table 4. Ideal Output Code⁽¹⁾ vs Input Signal
INPUT
SIGNAL
≥ 100% FS
0.001531% FS
0.001436% FS
0.000191% FS
0.000096% FS
0% FS
–0.3955% FS
IDEAL OUTPUT CODE
FORMAT = 1
1111 1111 1111 1111 1111
0000 0001 0000 0001 0000
0000 0001 0000 0000 1111
0000 0001 0000 0000 0010
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
IDEAL OUTPUT CODE
FORMAT = 0
1111 1111 1111 1111
0000 0001 0000 0001
0000 0001 0000 0000
0000 0001 0000 0000
0000 0001 0000 0000
0000 0001 0000 0000
0000 0000 0000 0000
(1) Excludes the effects of noise, INL, offset, and gain errors.
CLK
t_PDCDV
DVALID
t_HDDODV
t_PDDCDV
DCLK
DOUT
t_HDDODC
Input 64
MSB
Input 64 Input 63
LSB LSB
t_PDDCDO
Input 5 Input 4
LSB MSB
Input 2 Input 1
LSB MSB
Input 1
LSB
Input 64
MSB
Figure 27. Digital Interface Timing Diagram for Data Retrieval From a Single DDC264
Table 5. Timing for DDC264 Data Retrieval
SYMBOL
t_PDCDV
t_PDDCDV
t_HDDODV
t_HDDODC
t_PDDCDO ⁽¹⁾
DESCRIPTION
Propagation delay from falling edge of CLK to DVALID Low
Propagation delay from falling edge of DCLK to DVALID High
Hold time that DOUT is valid before the falling edge of DVALID
Hold time that DOUT is valid after falling edge of DCLK
Propagation delay from falling edge of DCLK to valid DOUT
MIN
TYP
10
5
400
4
(1) With a maximum load of one DDC264 (4pF typical) with an additional load of 5pF.
MAX
25
UNITS
ns
ns
ns
ns
ns
16
Copyright © 2006–2011, Texas Instruments Incorporated