DDC264 Datasheet, PDF (20/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
SBAS368C – MAY 2006 – REVISED JULY 2011
CONFIGURATION REGISTER
Read and Write Operations
The Configuration Register must be programmed
after power-up or a device reset. The DIN_CFG,
CLK_CFG, and RESET pins are used to write to this
register. When beginning a write operation, hold
CONV low and strobe RESET; see Figure 33. Then
begin shifting in the configuration data on DIN_CFG.
Data are written to the Configuration Register most
significant bit first. The data are internally latched on
the falling edge of CLK_CFG. Partial writes to the
Configuration Register are not allowed—make sure to
send all 16 bits when updating the register.
Optional readback of the Configuration Register is
available immediately after the write sequence.
During readback, 320 '0's, then the 16-bit
configuration data followed by a 4-bit revision ID and
the check pattern are shifted out on the DOUT pin on
the rising edge of DCLK. The check pattern can be
used to check or verify the DOUT functionality.
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NOTE: With Format = 1, the check pattern is 300
bits, with only the last 72 bits non-zero. This
sequence of outputs is repeated twice for each
DDC264 and daisy-chaining is supported in
configuration readback. Table 8 shows the check
pattern configuration during readback. Table 9 shows
the timing for the Configuration Register read and
write operations. Strobe CONV to begin normal
operation.
Table 8. Check Pattern During Readback
Format Bit
0
1
Check Pattern
(Hex)
180 0s,
30F066012480F6h
228 0s,
30F066012480F69055h
Total Readback
Bits
1024
1280
RESET
CLK_CFG
DIN_CFG
DCLK
t_RST
t_WTRST
(1)
Configuration Register Operations
t_WTWR
t_STCF
MSB
t_HDCF
LSB
Write Configuration Register Data
1
Read Configuration Register
and Check Pattern
(2)
320
Normal Operation
DOUT
CONV
MSB
LSB
(2)
320 0s
Configuration
Register
Data
Check Pattern
(1) CLK must be running during Configuration Register write and read operations.
(2) In 16-bit mode (FORMAT = 0), only 256 0s are read before the Configuration Register write and read operations.
Figure 33. Configuration Register Write and Read Operations
SYMBOL
t_WTRST
t_WTWR
t_STCF
t_HDCF
t_RST
Table 9. Timing for the Configuration Register Read/Write
DESCRIPTION
Wait Required from Reset High to First Rising Edge of CLK_CFG
Wait Required from Last CLK_CFG of Write Operation to
First DCLK of Read Operation
Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG
Hold Time for DIN_CFG After Falling Edge of CLK_CFG
Pulse Width for RESET Active
MIN
TYP
2
2
10
10
1
MAX
UNITS
μs
μs
ns
ns
μs
20
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