DDC264 Datasheet, PDF (13/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
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Integration Capacitors
There are four different capacitor configurations
available on-chip for both sides of every channel in
the DDC264. These internal capacitors are trimmed
in production to achieve the specified performance for
range error of the DDC264. The range control bits
(Range[1:0]) set the capacitor value for all integrators.
Consequently, all inputs and both sides of each input
always have the same full-scale range. Table 2
shows the capacitor value selected for each range
selection.
RANGE
0
1
2
3
Table 2. Range Selection
RANGE CONTROL BITS
Range[1]
Range[0]
C_F
0
0
3pF
0
1
12.5pF
1
0
25pF
1
1
37.5pF
INPUT
RANGE
–0.04 to
12.5pC
–0.2 to
50.0pC
–0.4 to
100pC
–0.6 to
150pC
Voltage Reference
The external voltage reference is used to reset the
integration capacitors before an integration cycle
begins. It is also used by the A/D converter while the
converter is measuring the voltage stored on the
integrators after an integration cycle ends. During this
sampling, the external reference must supply the
charge needed by the A/D converter. For an
integration time of 333μs, this charge translates to an
average VREF current of approximately 825μA. The
SBAS368C – MAY 2006 – REVISED JULY 2011
amount of charge needed by the A/D converter is
independent of the integration time; therefore,
increasing the integration time lowers the average
current. For example, an integration time of 800μs
lowers the average VREF current to 340μA.
It is critical that VREF be stable during the different
modes of operation (see Figure 22). The A/D
converter measures the voltage on the integrator with
respect to VREF. Because the integrator capacitors
are initially reset to VREF, any drop in VREF from the
time the capacitors are reset to the time when the
converter measures the integrator output introduces
an offset. It is also important that VREF be stable
over longer periods of time because changes in
VREF correspond directly to changes in the full-scale
range. Finally, VREF should introduce as little
additional noise as possible.
For these reasons, it is strongly recommended that
the external reference source be buffered with an
operational amplifier, as shown in Figure 23. In this
circuit, the voltage reference is generated by a
+4.096V reference. A low-pass filter to reduce noise
connects the reference to an operational amplifier
configured as a buffer. This amplifier should have low
noise and input/output common-mode ranges that
support VREF. Even though the circuit in Figure 23
might appear to be unstable because of the large
output capacitors, it works well for the OPA350. It is
not recommended that series resistance be placed in
the output lead to improve stability because this can
cause a drop in VREF, which produces large offsets.
+5V
0.47mF
1
2 ^1kW
REF3040
3
+
47mF
+5V
0.10mF
7
2
6
OPA350
3
0.10mF
4
0.7W
(1)
100mF
To VREF Pin on
the DDC264
0.7W
(1)
10mF
Near Each DDC
(1) Ceramic X5R capacitors are recommended.
Figure 23. Recommended External Voltage Reference Circuit for Best Low-Noise Operation
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