DDC264 Datasheet, PDF (14/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
SBAS368C – MAY 2006 – REVISED JULY 2011
Frequency Response
The frequency response of the DDC264 is set by the
front-end integrators and is that of a traditional
continuous time integrator, as shown in Figure 24. By
adjusting the integration time, t_INT, the user can
change the 3dB bandwidth and the location of the
notches in the response. The frequency response of
the A/D converter that follows the front-end integrator
is of no consequence because the converter samples
a held signal from the integrators. That is, the input to
the A/D converter is always a dc signal. The output of
the front-end integrators are sampled; therefore,
aliasing can occur. Whenever the frequency of the
input signal exceeds one-half of the sampling rate,
the signal folds back down to lower frequencies.
0
−10
−20
−30
−40
−50
0.1
1
t_INT
t_INT
10
100
t_INT
t_INT
Frequency
Figure 24. Frequency Response
DIGITAL INTERFACE
The digital interface of the DDC264 sends the digital
results via a synchronous serial interface that
consists of a data clock (DCLK), a valid data pin
(DVALID), a serial data output pin (DOUT), and a
serial data input pin (DIN). The integration and
conversion process is fundamentally independent of
the data retrieval process. Consequently, the CLK
and DCLK frequencies need not be the same, though
for best performance, it is highly recommended that
they be derived from the same clocking source to
keep the phase relationship constant. DIN is only
used when multiple converters are cascaded and
should be tied to DGND otherwise. Depending on
t_INT, CLK, and DCLK, it is possible to daisy-chain
multiple converters. This option greatly simplifies the
interconnection and routing of the digital outputs in
those applications where a large number of
converters are needed. Configuration of the DDC264
is set by a dedicated register addressed using the
DIN_CFG and CLK_CFG pins.
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System and Data Clocks (CLK and DCLK)
The system clock is supplied to CLK and the data
clock is supplied to DCLK. It is recommended that the
CLK pin be driven by a free-running clock source
(that is, do not start and stop CLK between
conversions). Make sure the clock signals are
clean—avoid overshoot or ringing. For best
performance, generate both clocks from the same
clock source. Disable DCLK by taking it low after the
data have been shifted out and while CONV is
transitioning.
When using multiple DDC264s, pay close attention to
the DCLK distribution on the printed circuit board
(PCB). In particular, make sure to minimize skew in
the DCLK signal because this can lead to timing
violations in the serial interface specifications. See
the Cascading Multiple Converters section for more
details.
Data Valid (DVALID)
The DVALID signal indicates that data are ready.
Data retrieval may begin after DVALID goes low. This
signal is generated using an internal clock divided
down from the system clock, CLK. The phase
relationship between this internal clock and CLK is
set when power is first applied and is random.
Because the user must synchronize CONV with CLK,
the DVALID signal has a random phase relationship
with CONV. This uncertainty is ±1/f_CLK. Polling
DVALID eliminates any concern about this
relationship. If the data readback is timed from
CONV, make sure to wait for the required amount of
time.
Reset (RESET)
The DDC264 is reset asynchronously by taking the
RESET input low, as shown in Figure 25. Make sure
the release pulse is a minimum of t_RST wide. It is very
important that RESET is glitch-free to avoid
unintentional resets. The Configuration Register must
be programmed immediately afterwards. After
programming the DDC264, wait at least four
conversions before using the data.
RESET
t_RST
Figure 25. Reset Timing
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