DDC264 Datasheet, PDF (15/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
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TIMING EXAMPLES
Figure 26 shows a few integration cycles beginning
after the device has been powered up, reset, and the
Configuration Register has been programmed. The
top signal is CONV and is supplied by the user. The
integration status trace indicates which side is
integrating. As described in the data sheet, DVALID
goes active low when data are ready to be retrieved
from the DDC264. It stays low until DCLK is taken
high and then back low by the user. The text below
the DVALID pulse indicates the side of the data
available to be read. The arrow is used to match the
data to the corresponding integration. Table 3 shows
the timing specifications for Figure 26.
SBAS368C – MAY 2006 – REVISED JULY 2011
Integration Time
The minimum t_INT depends on which device is being
used. The minimum time scales directly with the
internal clock frequency. For the DDC264C, with an
internal clock frequency of 5MHz, the minimum time
is 320μs. For the DDC264CK, with an internal clock
frequency of 10MHz, the minimum time is 166μs. If
the minimum integration time is violated, the DDC264
stops continuously integrating the input signal. To
return to normal operation (that is, continuous
integration) after a violation of the minimum t_INT
specification, perform three integrations that each last
for a minimum of 5000 internal clock periods. In other
words, integrate three times with each integration
lasting for at least 1ms when using an internal clock
frequency of 5MHz. During this time, ignore the
DVALID pin. Once the three integrations complete,
normal continuous operation resumes, and data can
be retrieved.
CONV
Integration
Status
t_INT
Integrate B
Integrate A
Integrate B
Integrate A
DVALID
t_DR
Side B
Data
Side A
Data
Figure 26. Integration Sequence Timing
Side B
Data
SYMBOL
DESCRIPTION
t_INT
Integration time
t_DR
Time until data ready
Table 3. Timing Specifications for Figure 26
DDC264C
Internal Clock Frequency = 5MHz
MIN
TYP
MAX
320
1,000,000
276.4 ± 0.4
DDC264CK
Internal Clock Frequency = 10MHz
MIN
TYP
MAX
160
138.2 ± 0.2
UNITS
μs
μs
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