DDC264 Datasheet, PDF (21/26 Pages) Texas Instruments – 64-Channel, Current-Input Analog-to-Digital Converter

DDC264
www.ti.com
SBAS368C – MAY 2006 – REVISED JULY 2011
Configuration Register Bit Assignments
Bit 15
Bit 14
Bit 13
0
0
Clkdiv
Bit 7
Bit 6
Bit 5
Version
0
0
Bit 12
0
Bit 4
Reserved
Bit 11
0
Bit 3
0
Bit 10
Range[1]
Bit 2
0
Bit 9
Range[0]
Bit 1
0
Bit 8
Format
Bit 0
Test
Bits 15:14
Bit 13
These bits must always be set to '0'.
Clkdiv
The Clkdiv input enables an internal divider on the system clock as shown in Table 10. When
Clkdiv = 1, the system clock is divided by 4. This configuration allows a system clock that is
faster by a factor of four, which in turn provides a finer quantization of the integration time,
because the CONV signal must be synchronized with the system clock for the best performance.
0 = Internal clock divider set to 1
1 = Internal clock divider set to 4
Bits 12:11
Bits 10:9
Bit 8
Bit 7
Bits 6:5
Bit 4
Bits 3:1
Bit 0
Table 10. Clkdiv Operation
Clkdiv Bit
0
1
CLK Divider Value
1
4
CLK Frequency
5MHz
20MHz
Internal Clock Frequency
5MHz
5MHz
These bits must always be set to '0'.
Range[1:0]
These bits set the full-scale range.
00 = Range 0 = 12.5pC
01 = Range 1 = 50.0pC
10 = Range 2 = 100.0pC
11 = Range 3 = 150.0pC
Format
Format selects how many bits are used in the data output word.
0 = 16-bit output
1 = 20-bit output
Version
This bit must be set to match the device being used.
Must be set to '0' for DDC264C.
Must be set to '1' for DDC264CK.
These bits must always be set to '0'.
Reserved
This bit is reserved and must be set to '0'.
These bits must always be set to '0'.
Test
When Test Mode is used, the inputs (IN1 through IN64) are disconnected from the DDC264
integrators to enable the user to measure a zero input signal regardless of the current supplied
to the inputs.
0 = TEST mode off
1 = TEST mode on
Copyright © 2006–2011, Texas Instruments Incorporated
21