DS99R103_14 Datasheet, PDF (18/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
www.ti.com
A termination resistor across DOUT± is also required for proper operation to be obtained. The termination
resistor should be equal to the differential impedance of the media being driven. This should be in the range of
90 to 132Ω. 100Ω is a typical value common used with standard 100Ω transmission media. This resistor is
required for control of reflections and also to complete the current loop. It should be placed as close to the
Serializer DOUT± outputs to minimize the stub length from the pins. To match with the deferential impedance on
the transmission line, the LVDS I/O are terminated with 100Ω resistors on Serializer DOUT± outputs pins.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5UI
apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce.
Applications Information
USING THE DS99R103 AND DS99R104
The DS99R103/DS99R104 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a
serial LVDS link up to 960 Mbps. Serialization of the input data is accomplished using an on-board PLL at the
Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clock information to
determine lock status and will indicate lock by asserting the LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. I_DD curve of CMOS
designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: TCLK jitter, V_DD noise (noise bandwidth and out-of-band noise)
• Media: ISI, V_CM noise
• Deserializer: V_DD noise
For a graphical representation of noise margin, please see Figure 16.
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100Ω. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance will be determined on data rates involved, acceptable
bit error rate and transmission medium.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live pluggable applications. The “Hot Inserted” operation on the
serial interface does not disrupt communication data on the active data lines. The automatic receiver lock to
random data “plug & go” live insertion capability allows the DS99R104 to attain lock to the active data stream
during a live insertion event.
18
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R103 DS99R104