DS99R103_14 Datasheet, PDF (16/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
www.ti.com
Serializer block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while
its PLL locks to the embedded clock information in serial data stream. Also, the Deserializer LOCK output will
remain low until its PLL locks to incoming data and sync-pattern on the RIN± pins.
2. The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special patterns.
The Serializer that is generating the stream to the Deserializer will automatically send random (non-
repetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded
clock within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the
incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit
expects a coded input bit stream. In order for the Deserializer to lock to a random data stream from the
Serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then
locks to it. Because this locking procedure is independent on the data pattern, total random locking duration
may vary. At the point when the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high
and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data
appearing on the outputs. The Deserializer’s LOCK pin is a convenient way to ensure data integrity is
achieved on receiver side.
DATA TRANSFER
After lock is established, the Serializer inputs DIN0–DIN23 are used to input data to the Serializer. Data is
clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer
outputs (DOUT±) are intended to drive point-to-point connections or limited multi-point applications.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1
bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits
in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on
transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This
bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data
integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically
performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 3 MHz to 40 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.12 Gbps maximum (84 Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times
the TCLK frequency. For example, if TCLK is , the serial rate is 40 x 28 = 1.12 Giga bits per second. Since only
24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 40
MHz, the payload data rate is 40 x 24 = 960 Mbps. TCLK is provided by the data source and must be in the
range of 3 MHz to 40 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as
shown in Figure 19. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The
DEN pin may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT(0-23), LOCK and RCLK outputs will each drive a maximum of 8 pF load with a 40 MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system must monitor the LOCK pin to determine whether data on the ROUT is valid.
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