DS99R103_14 Datasheet, PDF (15/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
www.ti.com
SNLS241D – MARCH 2007 – REVISED APRIL 2013
DS99R104 Deserializer Pin Descriptions (continued)
Pin
No.
17
Pin Name
LOCK
I/O
LVCMOS_O
2
RESRVD
LVCMOS_I
LVDS SERIAL INTERFACE PINS
41
RIN+
LVDS_I
42
RIN−
LVDS_I
POWER / GROUND PINS
39
VDDIR
VDD
40
VSSIR
GND
47
VDDPR0
VDD
46
VSSPR0
GND
45
VDDPR1
VDD
44
VSSPR1
GND
37
VDDR1
VDD
38
VSSR1
GND
36
VDDR0
VDD
35
VSSR0
GND
30
VDDOR1
VDD
29
VSSOR1
GND
20
VDDOR2
VDD
19
VSSOR2
GND
7
VDDOR3
VDD
8
VSSOR3
GND
Description
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
RESERVED – This pin MUST be tied LOW.
Receiver LVDS True (+) Input This input is intended to be terminated with a 100Ω load to the
RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100Ω load to the
RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
FUNCTIONAL DESCRIPTION
The DS99R103 Serializer and DS99R104 Deserializer chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput.
The DS99R103 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream
with embedded clock. The DS99R104 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data
over shielded twisted pair (STP) at clock speeds from 3 MHz to 40 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source. The
Deserializer synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock”
performance. The Deserializer recovers the clock and data by extracting the embedded clock information and
validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors
the incoming clock information, determines lock status, and asserts the LOCK output high when lock occurs.
Each has a power down control to enable efficient operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS99R103 and DS99R104 must be established before each device sends or receives data.
Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks
to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization
step.
1. When V_DD is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry. When V_DD reaches V_DD OK (2.2V) the PLL in
Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The
Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
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