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| DS99R103_14 Datasheet, PDF (11/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer | |||
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www.ti.com
DS99R103, DS99R104
SNLS241D â MARCH 2007 â REVISED APRIL 2013
RCLK
VDD/2
tLOW
tHIGH
VDD/2
ROUT [7:0]
tROS
(group 1)
VDD/2
Data Valid
Before RCLK
tROH
(group 1)
Data Valid
After RCLK
VDD/2
1/2 UI
tROS
(group 2)
ROUT [15:8], LOCK
VDD/2
Data Valid
Before RCLK
tROH
(group 2)
1/2 UI
Data Valid
After RCLK
VDD/2
1/2 UI
tROS
(group 3)
ROUT [23:16]
VDD/2
Data Valid
Before RCLK
tROH
(group 3)
1/2 UI
Data Valid
After RCLK
VDD/2
Figure 15. Deserializer Setup and Hold Times
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Sampling Position
( )tBIT
2
tBIT
(1UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
Copyright © 2007â2013, Texas Instruments Incorporated
Product Folder Links: DS99R103 DS99R104
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