DS99R103_14 Datasheet, PDF (1/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
www.ti.com
SNLS241D – MARCH 2007 – REVISED APRIL 2013
DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Check for Samples: DS99R103, DS99R104
FEATURES
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•2 3 MHz–40 MHz Clock Embedded and DC-
Balancing 24:1 and 1:24 Data Transmissions
• Capable to Drive Shielded Twisted-Pair Cable
• User Selectable Clock Edge for Parallel Data
on both Transmitter and Receiver
• Internal DC Balancing Encode/Decode –
Supports AC-Coupling Interface with no
External Coding Required
• Individual Power-Down Controls for both
Transmitter and Receiver
• Embedded Clock CDR (Clock and Data
Recovery) on Receiver and no External Source
of Reference Clock Needed
• All Codes RDL (Random Data Lock) to Support
Live-Pluggable Applications
• LOCK Output Flag to Ensure Data Integrity at
Receiver Side
• Balanced T_SETUP/T_HOLD Between RCLK and
RDATA on Receiver Side
• PTO (Progressive Turn-On) LVCMOS Outputs
to Reduce EMI and Minimize SSO Effects
• All LVCMOS inputs and control pins have
internal pulldown
• On-Chip Filters for PLLs on Transmitter and
Receiver
• Integrated 100Ω Input Termination on Receiver
• 4 mA Receiver Output Drive
• 48-Pin TQFP and 48-Pin WQFN Packages
• Pure CMOS .35 μm Process
• Power Supply Range 3.3V ± 10%
• Temperature Range −40°C to +85°C
• 8 kV HBM ESD Tolerance
DESCRIPTION
The DS99R103/DS99R104 Chipset translates a 24-
bit parallel bus into a fully transparent data/control
LVDS serial stream with embedded clock information.
This single serial stream simplifies transferring a 24-
bit bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and
connector size and pins.
The DS99R103/DS99R104 incorporates LVDS
signaling on the high-speed I/O. LVDS provides a low
power and low noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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