TLK1501_12 Datasheet, PDF (14/32 Pages) Texas Instruments – 0.6 TO 1.5 GBPS TRANSCEIVER

TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
reference clock input
The reference clock (GTX_CLK) is an external input clock that synchronizes the transmitter interface. The
reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data
on both its rising and falling edge, providing a serial data rate that is 20 times the reference clock.
operating frequency range
The TLK1501 is optimized for operation at a serial data rate of 1.2 Gbps. The TLK1501 may operate at a serial
data rate between 0.6 Gbps to 1.5 Gbps. The GTX_CLK must be within ±100 PPM of the desired parallel data
rate clock.
testability
The TLK1501 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled
so that an quiescent current test can be performed. The PRBS function allows for a BIST (built-in self-test).
loopback testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling
this terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can
be compared to the parallel input data for functional verification. (The external differential output is held in a
high-impedance state during the loopback testing.)
built-in self-test (BIST)
The TLK1501 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the
RX_ER/PRBS_PASS terminal.
power-on reset
Upon application of minimum valid power, the TLK1501 generates a power-on reset. During the power-on reset
the RXD, RX_ER, and RX_DV/LOS signal terminals to go to a high-impedance state. The RX_CLK is held low.
The length of the power-on reset cycle is dependent upon the REFCLK frequency, but is less than 1 ms.
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