DRV2510-Q1 Datasheet, PDF (12/32 Pages) Texas Instruments – DRV2510-Q1 3-A Automotive Haptic Driver for Solenoids and Voice Coils with Integrated Diagnostics

DRV2510-Q1
SLOS919A – JUNE 2016 – REVISED JUNE 2016
www.ti.com
Programming (continued)
slave address and the read-write (R/W) bit to start communication with a slave device. The master device then
waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock
period to indicate acknowledgment. When the acknowledgment occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible
devices share the same signals through a bidirectional bus using a wired-AND connection.
The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word
transfers, the master generates a stop condition to release the bus. Figure 8 shows a generic data-transfer
sequence.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull-up resistors
between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2510-
Q1 supply voltage, V_DD.
NOTE
The DRV2510-Q1 slave address is 0x6C (7-bit), or 1101100 in binary.
7-bit slave address
R/W A
8-bit register address (N)
A
8-bit register data for address
(N)
A
8-bit register data for address
(N)
A
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Start
Stop
Figure 8. Typical I²C Sequence
The DRV2510-Q1 device operates as an I²C-slave 1.8-V logic thresholds, but can operate up to the V_DD voltage.
The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5
(8-bit) for reading.
7.5.2 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.
During multiple-byte read operations, the DRV2510-Q1 device responds with data one byte at a time and begins
at the signed register. The device responds as long as the master device continues to respond with
acknowledges.
The DRV2510-Q1 supports sequential I²C addressing. For write transactions, a sequential I²C write transaction
has taken place if a register is issued followed by data for that register as well as the remaining registers that
follow. For I²C sequential-write transactions, the register issued then serves as the starting point and the amount
of data transmitted subsequently before a stop or start is transmitted determines how many registers are written.
7.5.3 Single-Byte Write
As shown in Figure 9, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the read-write bit. The read-write bit determines the direction of
the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I²C
device address and the read-write bit, the DRV2510-Q1 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the DRV2510-Q1 internal-memory address that is accessed. After
receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
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