DRV2510-Q1 Datasheet, PDF (11/32 Pages) Texas Instruments – DRV2510-Q1 3-A Automotive Haptic Driver for Solenoids and Voice Coils with Integrated Diagnostics

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DRV2510-Q1
SLOS919A – JUNE 2016 – REVISED JUNE 2016
Output Conditions
Load Diagnostics
OL Max
OL Min
SL Max
SL Min
Open Load
Open Load Detected
Open Load (OL)
Normal or Open Load
Detection Threshold May Be Detected
Normal
Load
Play Mode
Shorted Load (SL) Normal or Shorted Load
Detection Threshold
May Be Detected
Shorted
Load
Shorted Load
Detected
Figure 7. Load Diagnostic Reporting Thresholds
2. Faults During Load Diagnostics—If the device detects a fault (overtemperature, overvoltage, undervoltage)
during the load diagnostics test, the device exits the load diagnostics, which may result in a small transient
on the output.
7.4 Device Functional Modes
The DRV2510-Q1 device has multiple power states to optimize power consumption.
7.4.1 Operation in Shutdown Mode
The NRST pin of the DRV2510-Q1 device puts the device in a shutdown mode. When NRST is asserted (logic
low), all internal blocks of the device are off to achieve ultra low power. I²C is not operational in this mode and
the output is in Hi-Z state.
7.4.2 Operation in Standby Mode
The STDBY pin of the DRV2510-Q1 device puts the device in a standby mode. When STDBY is asserted (logic
high), some internal blocks of the device are off to achieve low power while preserving the ability to wake up
quickly to achieve low latency waveform playback.
7.4.3 Operation in Active Mode
The DRV2510-Q1 device is in active mode when it has a valid supply, and it is not in either shutdown or standby
modes. In this mode the DRV2510-Q1 device is fully on and reproducing at the output the input times the gain.
7.5 Programming
7.5.1 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with
the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the
SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period. Figure 8 shows a typical sequence. The master device generates the 7-bit
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