TMS320C6421_0711 Datasheet, PDF (91/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
3.7.3 Pin Multiplexing Details
This section discusses how to program each Pin Mux Block to select the desired peripheral functions.
The following steps can be used to determine pin muxing suitable for the application:
1. Understand the major configuration choices available for the specific application.
a. Device Major Configuration Choices: Figure 3-10 shown in Section 3.7, Multiplexed Pin
Configurations, provides a high-level view of the device pin muxing and can be used to determine
the possible mix of peripheral options for a specific application.
b. EMIFA Block Major Configuration Choices: The EMIFA block features extensive pin multiplexing to
accommodate a variety of applications. In addition to Figure 3-10, Section 3.7.3.11, EMIFA Block
Muxing, provides more details on the Major Configuration choices for this block.
2. See Section 3.7.3.1, Multiplexed Pins on C6421, for a summary of all the multiplexed pins on this
device and the pin mux group they belong to.
3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11,
EMIFA Block Muxing) for pin muxing details for a specific pin mux block.
a. For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that
peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals
Spanning Multiple Pin Mux Blocks .
For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2.
3.7.3.1 Multiplexed Pins on C6421
Table 3-19 summarizes all of the multiplexed pins on C6421, the pin mux group for each pin, and the
PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section
(Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA Block Muxing). For a description of the
PINMUX register fields, see Section 3.7.2.
SIGNAL
NAME
GP[54]
GP[53]
RMRXER/GP[52]
EM_A[13]/GP[51]
EM_A[14]/GP[50]
EM_A[15]/GP[49]
EM_A[16]/GP[48]
EM_A[17]/GP[47]
EM_A[18]/GP[46]
EM_A[19]/GP[45]
EM_A[20]/GP[44]
GP[43]
GP[42]
GP[41]
GP[40]
GP[39]
GP[38]
GP[37]
GP[36]
EM_R/W/GP[35]
EM_A[21]/GP[34]
RMRXD1/EM_CS5/GP[33]
Table 3-19. Multiplexed Pins on C6421
ZWT
NO.
A14
A13
A15
B10
A10
B11
C11
A11
D11
B12
C12
A12
B13
C13
D14
B14
C14
B15
C15
D13
D12
F19
ZDU
NO.
A18
A17
A19
A12
A13
C13
B13
B14
A14
C14
C15
A15
B15
B16
C18
A16
B17
B18
B19
C17
C16
J22
PINMUX DESCRIPTION
PINMUX GROUP
CONTROLLED BY PINMUX BIT FIELDS
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFASub-Block 0
EMIFA Sub-Block 0
EMIFASub-Block 0
EMIFA Sub-Block 0
EMIFASub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 0
EMIFA Sub-Block 1
-
-
RMII
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
GP[43:36] are standalone pins and are not
muxed with any other functions. They are
included in this table because they are grouped
in the EMIFA Sub-Block 0.
AEM
AEM
RMII, CS5SEL
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Device Configurations
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