TMS320C6421_0711 Datasheet, PDF (126/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
www.ti.com
6.4 Enhanced Direct Memory Access (EDMA3) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the C6421 device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
• Transfer to/from on-chip memories
– DSP L1D memory
– DSP L2 memory
• Transfer to/from external storage
– DDR2 SDRAM
– NAND flash
– Asynchronous EMIF (EMIFA)
• Transfer to/from peripherals/hosts
– VLYNQ
– HPI
– McBSP0
– McASP0
– PWM
– UART0
The EDMA supports two addressing modes: constant addressing and increment addressing. On the
C6421, constant addressing mode is not supported by any peripheral or internal memory. For more
information on these two addressing modes, see the TMS320C642x DSP Enhanced DMA (EDMA)
Controller User's Guide (literature number SPRUEM5).
6.4.1 EDMA3 Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 6-6 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the C6421 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the TMS320C642x DSP Enhanced DMA
(EDMA) Controller User's Guide (literature number SPRUEM5).
EDMA
CHANNEL
0-1
2
3
4
5
6
7
8
9
10
11
Table 6-6. C6421 EDMA Channel Synchronization Events⁽¹⁾
EVENT NAME
–
XEVT0
REVT0
–
–
–
–
–
–
AXEVTE0
AXEVTO0
EVENT DESCRIPTION
Reserved
McBSP0 Transmit Event
McBSP0 Receive Event
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
McASP0 Transmit Event Even
McASP0 Transmit Event Odd
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C642x DSP Enhanced
DMA (EDMA) Controller User's Guide (literature number SPRUEM5).
126 Peripheral Information and Electrical Specifications
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