TMS320C6421_0711 Datasheet, PDF (78/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
www.ti.com
For Host Boots (HPI Boot), the DSPBOOTADDR register is also used for communication between the
Host and the bootloader code during boot. For Host Boots, the DSPBOOTADDR register defaults to
Internal Bootloader ROM, and the C64x+ CPU is immediately released from reset so that it can begin
executing the bootloader code in this internal ROM. The bootloader code waits for the Host to boot the
device. Once the Host is done booting the device, it must write a new starting address into the
DSPBOOTADDR register, and follow with writing BOOTCMPLT.BC = 1 to indicate the boot is complete.
As soon as the bootloader code detects BOOTCMPLT.BC = 1, it instructs the CPU to jump to this new
DSPBOOTADDR address. At this point, the CPU continues the rest of the code execution starting from
the new DSPBOOTADDR location and the boot is completed.
3.5 Configurations At Reset
Some device configurations are determined at reset. The following subsections give more details.
3.5.1 Device and Peripheral Configurations at Device Reset
Table 2-7, BOOT Terminal Functions, lists the device boot and configuration pins that are latched at
device reset for configuring basic device settings for proper device operation. Table 3-10 summarizes the
device boot and configuration pins, and the device functions that they affect.
Table 3-10. Default Functions Affected by Device Boot and Configuration Pins
DEVICE BOOT AND
CONFIGURATION PINS
BOOT SELECTED
BOOTMODE[3:0]
Boot Mode
FASTBOOT
PLLMS[2:0]
AEM[2:0]
Fastboot
If FASTBOOT = 1, the
PLLMS[2:0] selects the
FASTBOOT PLL
Multiplier.
–
LENDIAN
–
PIN MUX CONTROL
GLOBAL SETTING
PERIPHERAL SETTING
PINMUX0/PINMUX1
Registers:
Based on
BOOTMODE[3:0], the
bootloader code programs
PINMUX0 and PINMUX1
registers to select the
appropriate pin functions
required for boot.
I/O Pin Power:
Based on
BOOTMODE[3:0], the
bootloader code programs
VDD3P3V_PWDN register
to power up the I/O pins
required for boot.
PSC/Peripherals:
Based on
BOOTMODE[3:0], the
bootloader code programs
the PSC to put
boot-related peripheral(s)
in the Enable State, and
programs the peripheral(s)
for boot operation.
–
Sets Device Frequency: –
Based on BOOTMODE,
FASTBOOT, and PLLMS;
the bootloader code
programs PLLC1.
–
Sets Device Frequency: –
Based on BOOTMODE,
FASTBOOT, and PLLMS;
the bootloader code
programs PLLC1.
PINMUX0.AEM:
–
Sets the default of this
field to control the EMIFA
Pinout Mode.
Affects the pin muxing in
EMIFA Sub-Block 0, 1,
and 3.
PSC/EMIFA:
The EMIFA module state
defaults to SwRstDisable
if AEM = 0; otherwise, the
EMIFA module state
defaults to Enable.
–
Device endianess
–
For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. For discussion situations where external pullup/pulldown resistors are required, see
Section 3.9.1, Pullup/Pulldown Resistors.
Note: The C6421 configuration inputs (BOOTMODE[3:0], FASTBOOT, PLLMS[2:0], AEM[2:0], and
LENDIAN) are multiplexed with other functional pins. These pins function as device boot and configuration
78
Device Configurations
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