TMS320C6421_0711 Datasheet, PDF (16/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
31
RESERVED
R-0000 0000 0000 0000
15
RESERVED
R- 0000 0000 0000 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Figure 2-2. L1PCFG Register
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16
3
2
0
L1PMODE
R/W-111 (7h)
Table 2-3. L1PCFG Register Bit Descriptions
Bit
Field Name
Description
31:3
RESERVED
Reserved. Read-only, writes have no effect.
L1PMODE select.
000 [0h] = L1P Cache Disabled
2:0
L1PMODE
001 [1h] = 4 KB
010 [2h] = 8 KB
011 [3h] = 16KB
100 [4h] – 111 [7h] = Reserved. Do Not Use.⁽¹⁾
(1) For proper C6421 device operation, only settings 000 [0h] through 011 [3h] are valid. To intialize L1P RAM/Cache to a valid cache
setting, the user must follow the sequence outlined in Section 3.8, Device Initialization Sequence After Reset. For more details, see the
TMS320C6424/21 Digital Signal Processor (DSP) Silicon Errata [Silicon Revisions 1.1 and 1.0] (literature number SPRZ252).
2.2.1.2 L1D Configuration Register (L1DCFG) Description
The L1D Configuration Register (L1DCFG) controls/defines the size of the L1D cache. The format and bit
field descriptions of the L1DCFG register for the C6421 are shown in Figure 2-3 and Table 2-4,
respectively.
31
16
RESERVED
R-0000 0000 0000 0000
15
RESERVED
R- 0000 0000 0000 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Figure 2-3. L1DCFG Register
3
2
0
L1DMODE
R/W-111 (7h)
16
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