TMS320C6421_0711 Datasheet, PDF (81/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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Bit
31:11
10:8
7:0
TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
Table 3-12. MSTPRI0 Register Description
Field Name
RESERVED
C64X+_CFGP
RESERVED
Description
Reserved. Read-only, writes have no effect.
C64X+_CFG master port priority in System Infrastructure.
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
31
27
26
25
24
23
22
21
20
19
RESERVED
RSV
RSV
HPIP
RSV
R-0000 0
R/W-100
R-0
R/W-100
R-0
15
3
RESERVED
R- 0000 0000 0000 0
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-6. MSTPRI1 Register— 0x01C4 0040
18
17
16
VLYNQP
R/W-100
2
1
0
EMACP
R/W-100
Bit
31:27
26:24
23
22:20
19
18:16
15:3
2:0
Table 3-13. MSTPRI1 Register Description
Field Name
RESERVED
RSV
RSV
HPIP
RSV
VLYNQP
RESERVED
EMACP
Description
Reserved. Read-only, writes have no effect.
Reserved. For proper device operation, the user must only write "100" to
these bits.
Reserved. Read-only, writes have no effect.
HPI master port priority in System Infrastructure.
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
VLYNQ master port priority in System Infrastructure.
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
EMAC master port priority in System Infrastructure.
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
3.6.2 Peripheral Selection After Device Reset
After device reset, most peripheral configurations are done within the peripheral’s registers. This section
discusses some additional peripheral controls in the System Module. For information on multiplexed pin
controls that determine what peripheral pins are brought out to the pins, see Section 3.7, Multiplexed Pin
Configurations.
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Device Configurations
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