TMS320C6421_0711 Datasheet, PDF (144/223 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007
www.ti.com
• Low Group: These pins are low by default, and remain low until configured otherwise by their
respective peripheral (after the peripheral is enabled by the PSC).
• High Group: These pins are high by default, and remain high until configured otherwise by their
respective peripheral (after the peripheral is enabled by the PSC).
• Z/Low Group (Z-to-Low Group): These pins are 3-stated when device-level global reset source (e.g.,
POR, RESET or Max Reset) is asserted. When the reset source is deasserted, these pins drive a logic
low.
• Z/High Group (Z-to-High Group): These pins are 3-stated when device-level global reset source
(e.g., POR, RESET or Max Reset) is asserted. When reset source is deasserted, these pins drive a
logic high.
• Clock Group: These clock pins are toggling by default. They paused momentarily before RESETOUT
is deasserted (high). The only pin in the Clock Group is CLKOUT0.
This is a list of possible default peripherals and how they control the pins during reset:
• GPIO: All GPIO pins behave according to Z Group.
Note: The following EMIFA list only includes pins that can default to function as EMIFA signals.
• EMIFA: These EMIFA signals are multiplexed with boot and configuration pins: EM_A[4], EM_A[2:0],
EM_BA[0], EM_BA[1]; therefore, they are forced 3-stated throughout RESETOUT.
– Z+/Low Group: EM_A[4], EM_A[2:0]
– Z+/High Group: EM_BA[0], EM_BA[1], EM_OE, EM_WE
– Z+/Invalid Group: EM_D[7:0]
– Z/Low Group: EM_A[21:5], EM_A[3], EM_R/W
– Z/High Group: EM_CS2
– Z Group: EM_WAIT
• DDR2 Memory Controller:
– Clock Group: DDR_CLK, DDR_CLK
– DDR2 Z Group: DDR_DQM[1:0], DDR_DQS[1:0], DDR_D[15:0]
– DDR2 Low Group: DDR_CKE, DDR_BS[2:0], DDR_A[12:0]
– DDR2 High Group: DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
• I2C: All I2C pins behave according to Z Group.
• JTAG: TDO, EMU0, and EMU1 pins behave according to Z Group. TCK, TDI, TMS, and TRST are
input-only pins.
• Clock: CLKOUT0
For more information on the pin behaviors during device-level global reset, see Figure 6-7 and Figure 6-8
in Section 6.5.9, Reset Electrical Data/Timing.
144 Peripheral Information and Electrical Specifications
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