THS10064 Datasheet, PDF (9/41 Pages) Texas Instruments – 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
detailed description
reference voltage
The THS10064 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to
3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS10064 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
analog-to-digital converter
The THS10064 uses a 10-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages,
which achieves a high sample rate with low power consumption. The THS10064 distributes the conversion over
several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device
passes the results from stage to stage. This distributed conversion requires a small fraction of the number of
comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages
permits the first stage to operate on a new input sample while the second through the eighth stages operate
on the seven preceding samples.
conversion modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the
conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In
the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table
1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
3 single-ended channels
4 single-ended channels
1 differential channel
2 differential channels
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
NUMBER OF
CHANNELS
1
2
3
4
1
2
2
3
MAXIMUM CONVERSION
RATE PER CHANNEL
6 MSPS
3 MSPS
2 MSPS
1.5 MSPS
6 MSPS
3 MSPS
3 MSPS
2 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
+ fc
6 MSPS
# channels
Table 2 shows the maximum conversion rate in the single conversion mode.
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