THS10064 Datasheet, PDF (8/41 Pages) Texas Instruments – 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
timing specifications, AV_DD = 5 V, BV_DD = DV_DD = 3.3 V, V_REF = internal, C_L < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
td(DATA_AV)
td(o)
tpipe
Delay time
Delay time
Latency
5
ns
5
ns
5
CONV
CLK
timing specification of the single conversion mode^†
PARAMETER
tc
Clock cycle of the internal clock oscillator
tw1
Pulse width, CONVST
tdA
Aperture time
t2
Time between consecutive start of single conversion
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 1
† _{Timing parameters are ensured by design but are not tested.}
TEST CONDITIONS
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
3 analog inputs, TL = 3
4 analog inputs, TL = 4
1 analog input, TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
MIN
159
1.5×tc
2×tc
3×tc
4×tc
5×tc
TYP
MAX
167
175
1
6×tc
7×tc
8×tc
9×tc
3×t2 +6×tc
t2 +7×tc
t2 +8×tc
t2 +9×tc
7×t2 +6×tc
3×t2 +7×tc
2×t2 +8×tc
2×t2 +9×tc
13×t2 +6×tc
5×t2 +7×tc
3×t2 +8×tc
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
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