THS10064 Datasheet, PDF (15/41 Pages) Texas Instruments – 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
Reading data from the FIFO
The THS10064 informs the connected processor via the digital output DATA_AV (data available) that a block
of conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger
level. The selectable trigger levels depend on the number of selected analog input channels. For example, when
choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate
the principle of reading the data (the READ signal is asynchronous to CONV_CLK).
In Figure 7, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 7. Trigger Level 1 Selected
In Figure 8, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 8. Trigger Level 4 Selected
In Figure 9, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 9. Trigger Level 8 Selected
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